Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract: An example embodiment relates to a method of forming a pattern structure, including forming an object layer on a substrate, and forming a hard mask on the object layer. A plasma reactive etching process is performed on the object layer using an etching gas including a fluorine containing gas and ammonia (NH3) gas together with oxygen gas to form a pattern. The oxygen gas is used for suppressing the removal of the hard mask during the etching process.

Abstract: A UV nanoimprint lithography process and its apparatus that are able to repeatedly fabricates nanostructures on a substrate (wafer, UV-transparent plate) by using a stamp that is as large as or smaller than the substrate in size are provided. The apparatus includes a substrate chuck for mounting the substrate; a stamp made of UV-transparent materials and having more than two element stamps, wherein nanostructures are formed on the surface of each element stamp; a stamp chuck for mounting the stamp; a UV lamp unit for providing UV light to cure resist applied between the element stamps and the substrate; a moving unit for moving the substrate chuck or the stamp chuck to press the resist with the element stamps and substrate; and a pressure supply unit for applying pressurized gas to some selected regions of the substrate to help complete some incompletely filled element stamps.

Abstract: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic material precursor coating layer to a mold patterned to have a protrusion and depression structure; forming the metal oxide thin film pattern by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer to cure it; and removing the patterned mold from the metal oxide thin film pattern.

Abstract: A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: The present invention relates to a micro/nano imprint lithography technique and in particular, to a stamp that is used in an UV-micro/nano imprint lithography process or thermal micro/nano imprint lithography process and a method for fabricating the stamp. The method for fabricating a stamp for micro/nano imprint lithography of the present invention includes i) depositing a thin film of diamond-like carbon on a substrate, ii) applying resist on the diamond-like carbon thin film, iii) patterning the resist, iv) etching the diamond-like carbon thin film by using the resist as a protective layer, and v) removing the resist.

Abstract: A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic material precursor coating layer to a mold patterned to have a protrusion and depression structure; forming the metal oxide thin film pattern by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer to cure it; and removing the patterned mold from the metal oxide thin film pattern.

Abstract: Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract: A UV nanoimprint lithography process and its apparatus that are able to repeatedly fabricates nanostructures on a substrate (wafer, UV-transparent plate) by using a stamp that is as large as or smaller than the substrate in size are provided. The apparatus includes a substrate chuck for mounting the substrate; a stamp made of UV-transparent materials and having more than two element stamps, wherein nanostructures are formed on the surface of each element stamp; a stamp chuck for mounting the stamp; a UV lamp unit for providing UV light to cure resist applied between the element stamps and the substrate; a moving unit for moving the substrate chuck or the stamp chuck to press the resist with the element stamps and substrate; and a pressure supply unit for applying pressurized gas to some selected regions of the substrate to help complete some incompletely filled element stamps.

Abstract: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit config

Abstract: A UV nanoimprint lithography process and its apparatus that are able to repeatedly fabricates nanostructures on a substrate (wafer, UV-transparent plate) by using a stamp that is as large as or smaller than the substrate in size are provided. The apparatus includes a substrate chuck for mounting the substrate; a stamp made of UV-transparent materials and having more than two element stamps, wherein nanostructures are formed on the surface of each element stamp; a stamp chuck for mounting the stamp; a UV lamp unit for providing UV light to cure resist applied between the element stamps and the substrate; a moving unit for moving the substrate chuck or the stamp chuck to press the resist with the element stamps and substrate; and a pressure supply unit for applying pressurized gas to some selected regions of the substrate to help complete some incompletely filled element stamps.

Abstract: A magnetic memory device includes a pinning layer, a pinned layer, an insulation layer, which are sequentially stacked on a semiconductor substrate. The magnetic memory device further includes a free layer disposed on the insulation layer, a capping layer disposed on the free layer and an MR (magnetoresistance) enhancing layer interposed between the free layer and the capping layer. The MR enhancing layer is formed of at least one anti-ferromagnetic material.

Abstract: A magnetic memory device and a method of fabricating the same. The magnetic memory device includes a free layer, a write element, and a read element. The write element changes the magnetization direction of the free layer, and the read element senses the magnetization direction of the free layer. Herein, the write element includes a current confinement layer having a width smaller than the minimum width of the free layer to locally increase the density of a current flowing through the write element.