Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Abstract: A data journaling method in a solid state storage device, the method including: receiving a read request; determining whether updated data mapping for the read request is located in at least one of a volatile journal and a nonvolatile journal using a Bloom filter; searching the volatile journal if the updated data mapping for the request is located in the Bloom filter, and then, searching the nonvolatile journal if the updated data mapping for the request is not found in the volatile journal; and stopping the search when the updated data mapping is found.

Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

Abstract: A storage device includes a nonvolatile memory device including a plurality of memory cells, the memory cells divided into a plurality of pages, and a controller configured to control the nonvolatile memory device. The storage device is configured to collect two or more write data groups to be written to two or more pages, to simultaneously perform a common write operation with the two or more pages based on the two or more write data groups, and to sequentially perform an individual write operation with each of the two or more pages based on the two or more write data groups.

Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

Abstract: A method of encrypting unencrypted digital content includes measuring an analog value associated with a physical property of interested cells of a memory array; digitizing the measured analog value to generate a response key; generating an encryption key based at least on the response key; encrypting the unencrypted digital content to generated encrypted digital content based on the encryption key; and storing the encrypted digital content.

Abstract: A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

Abstract: A controller for a display device includes an adjuster and a compensator. The adjuster adjusts at least one parameter of a modeling equation based on a measured current of a pixel. The modeling equation including the at least one adjusted parameter is indicative of a real time degree of degradation of the pixel. The compensator compensates for image data corresponding to emission of light from the pixel.

Abstract: An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (?1, . . . , ?r?1) to a Groebner basis for (?1, . . . , ?r), wherein ?r is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.

Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

Abstract: At least one example embodiment discloses a method of soft-decision Wu decoding a code. The code is one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code. The module is a sub-module of at least a first extension module and a second extension module. The first extension module is defined by a set of first type constraints and the second extension module is defined by a set of second type constraints. The first type constraints are applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints are applicable to the first interpolation algorithm. The method further includes determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.

Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.

Abstract: A memory device includes a nonvolatile memory and a memory controller. The memory controller receives first data from a host file system; stores the first data in a first physical block of the nonvolatile memory identified by a first physical page number (PPN); associates the first PPN with a first virtual page number (VPN); and communicates the first VPN to the host file system in response to receiving the first data.

Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

Abstract: An apparatus for polar coding includes an encoder circuit that implements a transformation c=u1N-sBN-s{tilde over (M)}n, where u1N-s, BN-s, {tilde over (M)}n, and C are defined over a Galois field GF(2k), k>1, N=2k, s<N, u1N-s=(u1, . . . , uN-s) is an input vector of N-s symbols over GF(2k), BN-s is a permutation matrix, {tilde over (M)}n=((N?s) rows of Mn=), the matrix M1 is a pre-defined matrix of size q×q, 2<q, N=qn and n?1, and C is a codeword vector of N-s symbols. A decoding complexity of C is proportional to a number of symbols in C. The apparatus further includes a transmitter circuit that transmits codeword C over a transmission channel.

Abstract: A method for storing data in a solid state device includes applying polar coding to generate channels including perfect channels, useless channels, and channels that are neither perfect nor useless. Some data is encoded using the perfect channels. A predetermined value is encoded using the useless channels. The other channels are divided into groups, depending upon a quality of each channel. Other data is encoded using the channels that are neither perfect nor useless using a different coding technique. This coding technique is applied to the same quality channels using several polar codewords, in parallel. Decoding is carried in a progressive parallel manner where the other coding technique assists the decoding of some polar codewords based on correct results from other polar codewords that were successfully decoded. The encoded data to be stored is written into the solid state device or transmitted.

Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.