Abstract: Provided is a method for producing SiC single crystal substrate including placing a SiC single crystal serving as a seed crystal and a SiC powder layer in a container in a state in which the SiC single crystal and the SiC powder layer are in contact with each other and performing a heat treatment by placing the container in an effective working zone of a firing furnace controlled to a temperature range within ±50° C. of a preset temperature to grow a SiC single crystal on the seed crystal.

Abstract: An anomaly detection server is provided. The anomaly detection server is a server for counteracting an anomalous frame transmitted on an on-board network of a single vehicle. The anomaly detection server acquires information about multiple frames received on one or multiple on-board networks of one or multiple vehicles, including the single vehicle. The anomaly detection server, acting as an assessment unit that, based on the information about the multiple frames and information about a frame received on the on-board network of the single vehicle after the acquisition of the information about the multiple frames, assesses an anomaly level of the frame received on the on-board network of the single vehicle.

Abstract: An electronic control unit is connected to a network in an in-vehicle network system. The electronic control unit includes a first control circuit and a second control circuit. The first control circuit is connected to the network via the second control circuit. The second control circuit performs a first determination process on a frame to determine conformity of the frame with a first rule. Upon determining that the frame conforms to the first rule, the second control circuit transmits the frame to the first control circuit. The first control circuit performs a second determination process on the frame to determine conformity of the frame with a second rule. The second rule is different from the first rule.

Abstract: In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.

Abstract: A coating device includes a coating roller configured to rotate in a rotation direction to apply a treatment liquid onto a sheet at an application position, and a contacting member in contact with a peripheral surface of the coating roller at a position downstream of the application position in the rotation direction.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: The reservoir tank includes a reservoir body which reserves a fluid in an inner portion thereof formed to be in a hollow box shape. The reservoir body includes a port extending outward, a reservoir chamber which reserves the fluid and a port chamber which volume is smaller than that of the reservoir chamber and is in fluid communication with the port and a first communication passage positioned at a portion lower than a changeable liquid surface of the fluid reserved in the reservoir chamber in a vertical direction and provided at the first partition portion to allow the fluid communication between the reservoir chamber and the port chamber and wherein the port chamber and the port are kept being a state in which they are filled with the fluid supplied from the reservoir chamber via the first communication passage.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Abstract: A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).

Abstract: The reservoir tank includes a reservoir body which reserves a fluid in an inner portion thereof formed to be in a hollow box shape. The reservoir body includes a port extending outward, a reservoir chamber which reserves the fluid and a port chamber which volume is smaller than that of the reservoir chamber and is in fluid communication with the port and a first communication passage positioned at a portion lower than a changeable liquid surface of the fluid reserved in the reservoir chamber in a vertical direction and provided at the first partition portion to allow the fluid communication between the reservoir chamber and the port chamber and wherein the port chamber and the port are kept being a state in which they are filled with the fluid supplied from the reservoir chamber via the first communication passage.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.

Abstract: A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.