Patents by Inventor Jun Matsushima

Jun Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170089979
    Abstract: It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 30, 2017
    Inventors: Hiroyuki IWATA, Jun MATSUSHIMA
  • Patent number: 8887015
    Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Iwata, Jun Matsushima
  • Patent number: 8597774
    Abstract: To provide a laser-marking film having a laser-marking ink layer capable of forming vivid images when it is irradiated with a laser beam for forming laser markings. A laser-marking film comprising a base film 1, a white underlying layer 3 formed on the base film 1, and an ink layer 5 for laser marking formed on the underlying layer 3, wherein the ink layer 5 contains, dispersed therein, an iron oxide as a laser beam-absorbing agent in an amount of 0.1 to 30 parts by weight per 100 parts by weight of a resin binder.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: December 3, 2013
    Assignee: Toyo Seikan Kaisha, Ltd.
    Inventors: Keiji Fukue, Atsushi Fukahori, Machiko Sugiyama, Shinji Tanaka, Jun Matsushima
  • Publication number: 20130095259
    Abstract: [Problems] To provide a laser-marking film having a laser-marking ink layer capable of forming vivid images when it is irradiated with a laser beam for forming laser markings. [Means for Solution] A laser-marking film comprising a base film 1, a white underlying layer 3 formed on the base film 1, and an ink layer 5 for laser marking formed on the underlying layer 3, wherein the ink layer 5 contains, dispersed therein, an iron oxide as a laser beam-absorbing agent in an amount of 0.1 to 30 parts by weight per 100 parts by weight of a resin binder.
    Type: Application
    Filed: July 15, 2010
    Publication date: April 18, 2013
    Applicant: TOYO SEIKAN KAISHA, LTD.
    Inventors: Keiji Fukue, Atsushi Fukahori, Machiko Sugiyama, Shinji Tanka, Jun Matsushima
  • Publication number: 20130019134
    Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 17, 2013
    Inventors: Hiroyuki IWATA, Jun MATSUSHIMA
  • Patent number: 8037384
    Abstract: A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 11, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takumi Hasegawa, Motoyuki Sato, Tomoji Nakamura, Nobuo Konami, Jun Matsushima
  • Patent number: 7743278
    Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 22, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yuri Ikeda, Yoshikazu Aoto, Jun Matsushima, Hiroyuki Sasaki, Tomoyoshi Ujii, Makoto Saen
  • Publication number: 20090172488
    Abstract: A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 2, 2009
    Inventors: Takumi Hasegawa, Motoyuki Sato, Tomoji Nakamura, Nobuo Konami, Jun Matsushima
  • Publication number: 20070226558
    Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.
    Type: Application
    Filed: November 16, 2006
    Publication date: September 27, 2007
    Inventors: Yuri Ikeda, Yoshikazu Aoto, Jun Matsushima, Hiroyuki Sasaki, Tomoyoshi Ujii, Makoto Saen
  • Patent number: 6574436
    Abstract: An image blur compensation device including a mechanism that can effectively reduce the effects of noise which becomes a problem in image blur compensation devices which are used in still cameras, video cameras, and the like. Particularly, the noise becomes a problem during position detection using a position sensitive device. The image blur compensation device includes an image blur compensation optical system to compensate for image blur arising due to blurring motion of an optical device, a position detection unit to detect the position of the image blur compensation optical system, an image blur compensation drive unit to drive the image blur compensation optical system based on the detection result of the position detection unit, and a power supply circuit which performs power supply to the position detection unit and the image blur compensation drive unit by a switching step-up control.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: June 3, 2003
    Assignee: Nikon Corporation
    Inventors: Tadashi Otani, Jun Matsushima
  • Publication number: 20030012565
    Abstract: An image blur compensation device including a mechanism that can effectively reduce the effects of noise which becomes a problem in image blur compensation devices which are used in still cameras, video cameras, and the like. Particularly, the noise becomes a problem during position detection using a position sensitive device. The image blur compensation device includes an image blur compensation optical system to compensate for image blur arising due to blurring motion of an optical device, a position detection unit to detect the position of the image blur compensation optical system, an image blur compensation drive unit to drive the image blur compensation optical system based on the detection result of the position detection unit, and a power supply circuit which performs power supply to the position detection unit and the image blur compensation drive unit by a switching step-up control.
    Type: Application
    Filed: September 12, 1996
    Publication date: January 16, 2003
    Inventors: TADASHI OTANI, JUN MATSUSHIMA
  • Publication number: 20010003197
    Abstract: Connected to a CD-RW drive (30) having an IDE apparatus interface (31), a speech apparatus output terminal (32), and a power supply apparatus input terminal (33), a converting unit (20) has an IDE unit interface (21), a speech unit input terminal (22), a power supply unit output terminal (23), a USB unit interface (24), a speech unit output terminal (25), and a power supply unit input terminal (26). The converting unit (20) comprises an IDE/USB converting circuit (27) connected between the IDE unit interface 21 and the USB unit interface (24). The IDE/USB converting circuit (27) carries out an interface conversion between an IDE interface and a USB interface. The converting unit (20) further comprises a noise filter (28) connected between the power supply unit input terminal (26) and the power supply unit output terminal (23). The speech unit input terminal (22) is directly connected to the speech unit output terminal (25).
    Type: Application
    Filed: November 30, 2000
    Publication date: June 7, 2001
    Inventors: Jun Matsushima, Tatsuya Inenaga
  • Patent number: 5794086
    Abstract: The display apparatus according to the present invention includes a display device which has a rotating indicator pointer and which displays information by rotationally driving the indicator pointer, an operating device which is capable of being operated in two manners for rotating the indicator pointer, and a drive control device which rotationally drives the rotating indicator pointer in the same rotational direction, whichever be the one of the two manners in which the operating device is operated.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 11, 1998
    Assignee: Nikon Corporation
    Inventors: Hiroshi Wakabayashi, Daiki Tsukahara, Yoshihiro Takeuchi, Akio Nishizawa, Jun Matsushima, Hiroyuki Tsuru
  • Patent number: 5696999
    Abstract: An image vibration reduction device for reducing an image vibration on an imaging surface includes a vibration reduction optical system movable to reduce the image vibration and constituting part of an imaging optical system, and a vibration reduction optical system displacement detector including a light-emission unit and a light-reception unit using an optical position detection element to optically detect a change in position of the vibration reduction optical system. The device also includes a light-emission amount automatic adjustment means for adjusting a light-emission amount of the light-emission unit at a predetermined time on the basis of an output from the light-reception unit.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: December 9, 1997
    Assignee: Nikon Corporation
    Inventors: Jun Matsushima, Tadashi Otani, Sueyuki Ohishi
  • Patent number: 5433045
    Abstract: A device to control vertical vibration of a building caused by seismic disturbance. Air springs are positioned and secured between the building foundation and the building superstructure to attenuate vertical vibration of the building. Vertical support rails are secured to the foundation and/or to the building superstructure on opposite sides of, and adjacent to, the air springs. Horizontal connecting brackets are rigidly secured to the air springs and slidably secured to the adjacent rails. The brackets restrain horizontal deflection of the air springs without interfering with vertical reciprocation of the air springs.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: July 18, 1995
    Assignees: Kajima Corporation, Yacmo Kabushiki Kaisha
    Inventors: Kenichi Yano, Hideo Hayashi, Ryuichi Kamimura, Masamitsu Miyamura, Jun Matsushima, Toru Kasai, Katsuhisa Kanda, Nobumitsu Funaki
  • Patent number: 5327692
    Abstract: A device to control vertical vibration of a building caused by seismic disturbance. Air springs are positioned and secured between the building foundation and the building superstructure to attenuate vertical vibration of the building. Vertical support rails are secured to the foundation and/or to the building superstructure on opposite sides of, and adjacent to, the air springs. Horizontal connecting brackets are rigidly secured to the air springs and slidably secured to the adjacent rails. The brackets restrain horizontal deflection of the air springs without interfering with vertical reciprocation of the air springs.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: July 12, 1994
    Assignees: Kajima Corporation, Yacmo Kabushiki Kaisha
    Inventors: Kenichi Yano, Hideo Hayashi, Ryuichi Kamimura, Masamitsu Miyamura, Jun Matsushima, Toru Kasai, Katsuhisa Kanda, Nobumitsu Funaki
  • Patent number: 4984474
    Abstract: A torque sensor for use in detecting torsion of a power steering device or the like of a vehicle.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: January 15, 1991
    Assignee: Copal Company Limited
    Inventors: Jun Matsushima, Tetsuto Kageyama, Shigekazu Nakamura, Kenji Wakazono