Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Abstract: The present disclosure provides a memory block and its control method. The method includes: performing row-selection operation on at least a portion of at least one row of multiple rows of word lines in the memory block to select at least a portion of at least one row of memory cells; performing column-selection operation on at least one column of memory cells of at least one of multiple memory subarrays to select at least one memory cells to perform a memory operation.

Abstract: A MEMS microphone is provided, comprising a substrate having a back cavity, and a plate capacitor structure arranged on the substrate, the plate capacitor structure being formed by a vibration diaphragm, a backplate and a support portion; wherein a pressure relief device is provided in the vibration diaphragm, a pressure maintaining channel is formed between the vibration diaphragm and the backplate; and the pressure relief device in the vibration diaphragm constitutes an inlet of the pressure maintaining channel.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to perform a maintenance operation involving a plurality of hosts of an information handling system cluster by: determining a score for each host based on a sum of working memory sizes for all active virtual machines executing on such host plus a sum of persistent storage sizes for all virtual machines stored on such host; based on the determined scores, selecting a first host for upgrading; migrating at least a portion of all virtual machines stored on the first host from the first host to one or more other hosts; and causing the first host to perform the maintenance operation.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to store a first set of data comprising an operating system in a first location; store a second set of data comprising application data in a second location; expose the first and second sets of data in a combined union mount filesystem; and create a backup of the second set of data, but not the first set of data, by creating a copy of the second location.

Abstract: A system may have a display that includes a plurality of light sources such as light-emitting diodes. The display may be an exterior display that is routinely operated in daytime conditions where ambient light levels are very high. To increase contrast in an exterior display, the display may include a sunlight blocking element. A static sunlight blocking element may include a louver film with asymmetric light blocking portions. The system may include an ambient light sensor that is configured to determine ambient light levels. Based on the detected ambient light level, control circuitry in the system may adjust one or more adjustable components in the display. The display may include an adjustable diffuser that has at least two states with different haze levels. The display may include an adjustable tint layer that has at least two states with different transmission levels.

Abstract: A power tool includes a brushless motor, including a stator and a rotor; an inverter circuit, including a plurality of switch components, where the plurality of switch components are configured to perform a switch action to control driving of the brushless motor; and a controller, electrically connected to the inverter circuit and the brushless motor, the controller including a load detection module configured to detect a parameter indicating a workload of the brushless motor. In response to the parameter being less than a set threshold, the controller is configured to control the brushless motor to maintain a first target rotational speed; and in response to the parameter being greater than or equal to a set threshold, the controller controls the brushless motor to maintain a second target rotational speed. The first target rotational speed may be greater than the second target rotational speed.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: A disclosed system is configured to bond a chip to a substrate and includes a chip processing subsystem that is configured to receive the chip and to expose the chip to a first plasma, and a substrate processing subsystem that is configured to receive the substrate and to expose the substrate to a second plasma. The system further includes a bonding subsystem that is configured to align the chip with the substrate, to force the chip and the substrate into direct mechanical contact with one another by application of a compressive force, and to apply heat to at least one of the chip or the substrate. Application of the compressive force and the heat thereby bonds the chip to the substrate. The first and second plasmas may include H2/N2, H2/Ar, H2/He, NH3/N2, NH3/Ar, or NH3/He and the chip and substrate may be maintained in a low oxygen environment.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: A channel allocation method and a related apparatus are disclosed. The method is for reducing a quantity of access points whose channels are to be switched and reducing an amount of calculation for channel switching. The method includes: obtaining interference degrees of a plurality of access points; and performing partial channel allocation based on the interference degrees. The partial channel allocation includes: retaining an operating channel of an access point in a first access point set, and reallocating an operating channel to an access point in a second access point set. The first access point set includes an access point whose interference degree is lower than a target degree in the plurality of access points, and the second access point set includes an access point whose interference degree reaches the target degree in the plurality of access points.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.