Abstract: A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.

Abstract: A display panel and a display are disclosed. A display panel has an active area and a peripheral area disposed adjacent to the active area and comprises a first substrate, a second substrate, a first insulating layer, a second insulating layer and an organic layer. The second substrate is disposed opposite the first substrate. The first insulating layer is disposed on the side of the first substrate facing the second substrate. The organic layer covers the first insulating layer. The second insulating layer covers the organic layer and includes at least a first opening which is disposed in the peripheral area and exposes the organic layer.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: A method for manufacturing display panel is disclosed, which comprises: (A) providing a substrate, an oxide semiconductor layer disposed on the substrate, and a gate electrode disposed on the substrate and corresponding to the oxide semiconductor layer; (B) forming a metal layer on the oxide semiconductor layer; (C) forming a photoresist on the metal layer, and etching the metal layer to form a source electrode and a drain electrode; (D) heating the photoresist and the photoresist covers at least partial of side walls of the source electrode and the drain electrode; (E) applying an alkaline solution on the substrate; and (F) removing the photoresist to expose the source electrode and the drain electrode.

Abstract: A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed.

Abstract: A thin-film transistor substrate is disclosed, which comprises a base layer; a semiconductor layer disposed on the base layer; a source electrode and a drain electrode disposed on the semiconductor layer; and a gate electrode disposed on the base layer and corresponding to the semiconductor layer; wherein the semiconductor layer includes a first region, a second region, and a third region, in which the first region corresponds to the gate electrode layer, the second region corresponds to the source electrode, and the third region corresponds to the drain electrode; and wherein the first region has a first thickness, the second region has a second thickness, and the third region has a third thickness, and the first thickness is greater than the second thickness or the third thickness.

Abstract: A display panel comprises a first substrate, a second substrate and an organic planarization layer. The first substrate has an active area and a non-active area disposed adjacent to the active area. The second substrate is disposed opposite the first substrate. The organic planarization layer is disposed on the first substrate facing the second substrate and includes at least a first through portion which is disposed in the non-active area and exposes a film layer under the organic planarization layer.

Abstract: A display panel and a display are disclosed. A display panel has an active area and a peripheral area disposed adjacent to the active area and comprises a first substrate, a second substrate, a first insulating layer, a second insulating layer and an organic layer. The second substrate is disposed opposite the first substrate. The first insulating layer is disposed on the side of the first substrate facing the second substrate. The organic layer covers the first insulating layer. The second insulating layer covers the organic layer and includes at least a first opening which is disposed in the peripheral area and exposes the organic layer.

Abstract: The present invention relates to a display device, comprising: a substrate comprising a display region and a non-display region surrounding the display region; a first conductive layer disposed on the substrate; a semiconductor layer disposed on the substrate and partially covering the first conductive layer; and a second conductive layer disposed on a top surface of the semiconductor layer; and there is a spacing between a first side of the semiconductor layer and a second side of the second conductive layer from a top view, wherein the first side of the semiconductor layer is adjacent to the second side of the second conductive layer; wherein the spacing in the display region is a first distance, the spacing in the non-display region is a second distance, and the first distance is smaller than the second distance.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: There is provided a semiconductor device including a first conductive layer, an insulating layer, a second conductive layer, a channel layer, a passivation layer and a third conductive layer. The insulating layer covers the first conductive layer. The second conductive layer is formed on the insulating layer and has an inner opening. The channel layer is formed on the inner opening of the second conductive layer to fully cover the inner opening. The passivation layer is formed upon the channel layer to cover the channel layer and has a contact hole inside the inner opening of the second conductive layer. The third conductive layer is formed in the contact hole.

Abstract: A vertical thin-film transistor structure includes a substrate, a source electrode, an insulation layer, a drain electrode, two first channel layers, a gate insulation layer and a gate electrode, which are stacked upward in that order on the substrate. The first channel layers are respectively disposed at two opposite ends of the drain electrode, and extend from the upper surface of the drain electrode to the upper surface of the source electrode respectively. Each of the first channel layers contacts the source electrode and the drain electrode. The gate insulation layer is disposed on the source electrode, the first channel layers and the drain electrode. The gate electrode is disposed on the gate insulation layer and covers the first channel layers. Therefore, the volume of the conventional thin-film transistor structure shrinks, and the ratio of the volume of the conventional thin-film transistor structure to that of a pixel structure decreases.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract: A thin-film transistor (TFT) device comprises a gate, a source, a drain, an insulation layer and an active area. The insulation layer electrically separates the gate from the source and the drain. The active area including a plurality of contacting areas contacting the source and the drain, respectively, and generates a channel including a channel width and a channel length. The active area includes a semiconductor material and has a plurality of active-area edges. In the direction parallel to the channel width, a distance between at least a contacting-area edge of the contacting areas and the active-area edge of the active area that is near to the contacting-area edge is larger than 2.5 ?m and less than or equal to 16 ?m. A TFT display apparatus is also disclosed.

Abstract: A disc clamping structure is provided. A fixing base is disposed on a turntable. A plurality of ball seats are disposed around a periphery of the fixing base, and each of the ball seats has an aperture. The balls are received in the ball seats. The elastic members are disposed within the fixing base. The balls are upwardly moved, and the height of the center point of the ball is adjusted according to the thickness of the disc when the disc is clamped on the turntable. A portion of the ball is projected from the aperture of the ball seat before clamping the disc.

Abstract: A vertical thin-film transistor structure includes a substrate, a source electrode, an insulation layer, a drain electrode, two first channel layers, a gate insulation layer and a gate electrode, which are stacked upward in that order on the substrate. The first channel layers are respectively disposed at two opposite ends of the drain electrode, and extend from the upper surface of the drain electrode to the upper surface of the source electrode respectively. Each of the first channel layers contacts the source electrode and the drain electrode. The gate insulation layer is disposed on the source electrode, the first channel layers and the drain electrode. The gate electrode is disposed on the gate insulation layer and covers the first channel layers. Therefore, the volume of the conventional thin-film transistor structure shrinks, and the ratio of the volume of the conventional thin-film transistor structure to that of a pixel structure decreases.