Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a P-type vertical field effect transistor (VFET) including a first channel region and a first top source/drain region sequentially stacked on a substrate in a vertical direction, an N-type VFET including a second channel region and a second top source/drain region sequentially stacked on the substrate in the vertical direction, and a top contact layer contacting both the first top source/drain region and the second top source/drain region.

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.

Abstract: Provided are integrated circuits including a plurality of standard cells aligned along a plurality of rows. The integrated circuit includes first standard cells aligned on the first row and including first conductive patterns to which a first supply voltage is applied in a conductive layer and second standard cells aligned on the second row which is adjacent to the first row in the conductive layer and including second conductive patterns to which the first supply voltage is applied in the conductive layer. A pitch between the first conductive patterns and the second conductive patterns may be less than a pitch provided by single-patterning.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) having a first conductivity type, and a second VFET having a second conductivity type. The first VFET may include a first top source/drain region, a first channel region, and a first bottom source/drain region. The second VFET may include a second top source/drain region, a second channel region, and a second bottom source/drain region. The standard cells may also include a conductive line that is electrically connected to the first top source/drain region or the first bottom source/drain region and is electrically connected to the second bottom source/drain region. The standard cell may be configured to output an output signal thereof through the conductive line.

Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may a first vertical field effect transistor (VFET) having a first conductivity type, a second VFET having a second conductivity type, and a third VFET having the first conductivity type. The first VFET may include a first channel region protruding from a substrate, and the first channel region has a first length. The second VFET may include a second channel region protruding from the substrate, and the second channel region has a second length. The third VFET may include a third channel region protruding from the substrate. The first channel region, the second channel region, and third channel region may be spaced apart from each other and may be sequentially arranged along a direction, and the second length may be greater than 1.5 times the first length.

Abstract: Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.

Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X?1)-contacted poly pitch (CPP) circuit, which is (X?1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X?1)-CPP circuit, X being an integer greater than 1.

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.