Patents by Inventor Jung-Ho Park

Jung-Ho Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220352050
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
  • Publication number: 20220262696
    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
  • Patent number: 11404346
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 2, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
  • Publication number: 20220216068
    Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
  • Patent number: 11328970
    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 10, 2022
    Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
  • Patent number: 11322368
    Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
  • Publication number: 20220104405
    Abstract: A display device includes a flexible display portion, a case which accommodates the display portion, and a blocking layer which is disposed between the display portion and the case. The blocking layer includes a plurality of nanolines.
    Type: Application
    Filed: July 15, 2021
    Publication date: March 31, 2022
    Inventors: Jung Ho PARK, Gyung-Kook KWAK, Jeong Il YOO, Sung Chul CHOI
  • Publication number: 20220077041
    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 10, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gwangjae JEON, Jung-Ho PARK, Seokhyun LEE, Yaejung YOON
  • Publication number: 20220044992
    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.
    Type: Application
    Filed: October 24, 2021
    Publication date: February 10, 2022
    Inventors: Jung Ho PARK, Jong Youn KIM, Min Jun BAE
  • Patent number: 11233894
    Abstract: An electronic device is provided that includes a wireless communication device configured to connect with wireless external devices. The electronic device obtains information regarding the wireless external devices. Before and after a call connection event, it is determined whether each of the wireless external devices includes a microphone based on the information. In response to receiving the call connection event, when it is determined that only one of the wireless external devices includes a microphone, an audio input is obtained from the one of the wireless external devices that includes the microphone. In response to receiving the call connection event, when it is determined that at least two of the wireless external devices each include a respective microphone, an audio input is selectively obtained from a microphone of one of the at least two of the plurality of wireless external devices.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: January 25, 2022
    Inventors: Sang-Kyu Park, Seung-Yup Lee, Jung-Ho Park, Soo-Ho Song
  • Patent number: 11177205
    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Ho Park, Jong Youn Kim, Min Jun Bae
  • Patent number: 11166368
    Abstract: A printed circuit board that includes a base layer having a first surface and a second surface opposing each other. A first structure is disposed on the first surface of the base layer. The first structure includes a first plate structure. A first connection structure is disposed on a same plane as the first plate structure and is spaced apart from the first plate structure. The first plate structure includes first openings. At least some of the first openings are linear openings having a line shape.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Ho Park, In Won O, Hak Jun Kim
  • Patent number: 11121064
    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
  • Publication number: 20210257223
    Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: August 19, 2021
    Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
  • Patent number: 11001318
    Abstract: A rubber track to prevent occurrence edge-cuts and improve traction force even in the soft ground is disclosed. The rubber track is configured by first lugs which are formed at equal intervals on one side of the inside and the outside in a traveling direction on a surface coming into contact with the ground and have first grooves formed in a width direction; and second lugs which are formed at equal intervals on the other side of the inside and the outside in a traveling direction on a surface coming into contact with the ground and have second grooves formed in the traveling direction.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 11, 2021
    Assignee: DRB INDUSTRIAL CO., LTD.
    Inventors: Yoon-Tae Nam, Jung-Ho Park
  • Publication number: 20210066149
    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.
    Type: Application
    Filed: May 5, 2020
    Publication date: March 4, 2021
    Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
  • Publication number: 20210057317
    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.
    Type: Application
    Filed: March 16, 2020
    Publication date: February 25, 2021
    Inventors: Jung-Ho PARK, Da Hye KIM, Jin-Woo PARK, Jae Gwon JANG
  • Publication number: 20210050298
    Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.
    Type: Application
    Filed: May 14, 2020
    Publication date: February 18, 2021
    Inventors: Da Hye KIM, Dong Kyu KIM, Jung-Ho PARK
  • Publication number: 20210025204
    Abstract: A motor-driven door ratchet includes a catch part configured to lock a vehicle door to a vehicle body by being caught by a striker mounted on the vehicle body. A door locking and release part includes a main motor and is configured to allow the catch part to be locked or released from the striker. An inside emergency operation lever is connected to an inside handle installed in the vehicle door and is configured to be rotated by receiving a manipulation force to allow the vehicle door to be opened by applying torque to the catch part. An outside emergency operation lever is connected to an outside handle installed in the vehicle door and is configured to be rotated by receiving a manipulation force to allow the vehicle door to be opened by applying torque to the catch part.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 28, 2021
    Inventors: Jinwoo Nam, Kyoung Taek Kwak, Jungho Han, Hyuk Noh, Jung-Ho Park, Ki Ryun Ahn, Jin-Bok Lee, Ji-Woo Joo
  • Publication number: 20210028137
    Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.
    Type: Application
    Filed: February 20, 2020
    Publication date: January 28, 2021
    Inventors: GWANGJAE JEON, DONGKYU KIM, JUNG-HO PARK, YEONHO JANG