Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection.

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: The application provides an apparatus, a system, a detector and a method. The apparatus includes: a power supply voltage detector, including: N buffers, an input terminal of a first buffer being connected to a clock signal, output terminals of other buffers being connected to the input terminal of an adjacent buffer; N latch chains, each of which includes M latches, a clock input terminal of each latch being connected to a clock signal, a D terminal of a first latch of each latch chain being connected to the output terminal of a corresponding buffer, Q terminals of other latches being connected to the D terminal of an adjacent latch, M and N being positive integers, the D terminal of each latch being connected to an area where a power supply voltage is to be detected; and a voltage regulation module connected to the Q terminal of each latch.

Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

Abstract: A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.

Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.

Abstract: A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: An apparatus and a method to adjust a source voltage based on an operating voltage response are provided. The apparatus includes a circuit configured to change state from a first state to a second state comprising receiving an operating voltage from a power source through a power distribution network. The apparatus further includes a sensor configured to measure an operating voltage response to the circuit changing state to receiving the operating voltage. The apparatus further includes a control circuit configured to adjust a source voltage at the power source based on the operating voltage response measured by the sensor. The method includes changing a state to receiving an operating voltage from a power source through a power distribution network, measuring an operating voltage response to the changing state to receiving the operating voltage, and adjusting the source voltage at the power source based on the measured operating voltage response.

Abstract: An apparatus for sensing distributed load currents provided by power gating circuit. The apparatus includes a power gating circuit including a set of bulk transistors coupled in series with a set of circuits between first and second voltage rails. The apparatus includes a current sensor with a first ring oscillator, a first frequency-to-code (FTC) converter, a second ring oscillator, a second FTC converter, and a subtractor. The first ring oscillator includes a first set of one or more inverters configured to receive a first voltage at a node between the power gating circuit and the first circuit, and a second set of one or more inverters configured to receive a second voltage at a second node between the power gating circuit and the second circuit. The first ring oscillator is configured to generate a signal including a frequency related to the voltage drops across the first and second sets of transistors.

Abstract: Aspects of the disclosure are directed to a low noise physically unclonable function (PUF) cell. In accordance with one aspect, the low noise physically unclonable function (PUF) cell includes a first inverter, wherein the first inverter is configured in a negative feedback configuration; and a second inverter coupled to the first inverter in a series configuration, wherein the second inverter is configured in a first open loop configuration.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for sensing a temperature. For example, certain aspects of the present disclosure may provide a temperature sensing circuit. The temperature sensing circuit may include a first current mirror having a first branch coupled to a first transistor, a resistive element coupled between a source of the first transistor and a reference potential, and a second current mirror having a first branch coupled to a second transistor. In certain aspects, a source of the second transistor may be coupled to the reference potential, and a gate of the first transistor may be coupled to a gate of the second transistor. In certain aspects, the temperature sensing circuit may also include an oscillator having an input coupled to a third transistor of the second current mirror.

Abstract: An apparatus for sensing distributed load currents provided by power gating circuit. The apparatus includes a power gating circuit including a set of bulk transistors coupled in series with a set of circuits between first and second voltage rails. The apparatus includes a current sensor with a first ring oscillator, a first frequency-to-code (FTC) converter, a second ring oscillator, a second FTC converter, and a subtractor. The first ring oscillator includes a first set of one or more inverters configured to receive a first voltage at a node between the power gating circuit and the first circuit, and a second set of one or more inverters configured to receive a second voltage at a second node between the power gating circuit and the second circuit. The first ring oscillator is configured to generate a signal including a frequency related to the voltage drops across the first and second sets of transistors.

Abstract: In one embodiment, a method for measuring current comprises generating a sensor current based on a current being measured. The method also comprises converting a combined current into a first frequency, wherein the combined current is a sum of the sensor current and a common-mode current, and converting the first frequency into a first count value. The method further comprises converting the common-mode current into a second frequency, converting the second frequency into a second count value, and subtracting the second count value from the first count value to obtain a current reading.

Abstract: Systems and methods for sensing temperature on a chip are described herein. In one embodiment, a temperature sensor comprises a first transistor having a gate, a second transistor having a gate coupled to the gate of the first transistor, and a bias circuit configured to bias the gates of the first and second transistors such that the first and second transistors operate in a sub-threshold region, and to generate a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor. The temperature sensor also comprises an analog-to-digital converter (ADC) configured to convert the current into a digital temperature reading.