Patents by Inventor Junya Matsuno
Junya Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352093Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.Type: ApplicationFiled: March 3, 2023Publication date: November 2, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Yasuhiro HIRASHIMA, Toshiyuki KOUCHI
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Publication number: 20230223938Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Patent number: 11637555Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: January 31, 2022Date of Patent: April 25, 2023Assignee: Kioxia CorporationInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Patent number: 11568935Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: GrantFiled: May 25, 2021Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi, Kensuke Yamamoto, Masato Dome, Kei Shiraishi, Junya Matsuno, Kenro Kubota
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Publication number: 20230028971Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Publication number: 20230018613Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11495308Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Junya Matsuno, Kenro Kubota, Masato Dome, Kensuke Yamamoto, Kei Shiraishi, Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi
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Patent number: 11495307Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masato Dome, Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota
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Publication number: 20220158639Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Publication number: 20220093185Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Publication number: 20220093188Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11277134Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: August 26, 2020Date of Patent: March 15, 2022Assignee: KlOXIA CORPORATIONInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Publication number: 20220059165Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: ApplicationFiled: May 25, 2021Publication date: February 24, 2022Applicant: Kioxia CorporationInventors: Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI, Kensuke YAMAMOTO, Masato DOME, Kei SHIRAISHI, Junya MATSUNO, Kenro KUBOTA
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Patent number: 11232051Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: GrantFiled: August 21, 2020Date of Patent: January 25, 2022Assignee: Kioxia CorporationInventors: Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota, Masato Dome
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Publication number: 20210271615Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: ApplicationFiled: August 21, 2020Publication date: September 2, 2021Applicant: Kioxia CorporationInventors: Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA, Masato DOME
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Publication number: 20210226632Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: August 26, 2020Publication date: July 22, 2021Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Patent number: 10798858Abstract: After one suction nozzle turns from one arrangement pitch ahead of a work position toward the work position and immediately before the suction nozzle starts descent at the work position, an image of a side portion of the suction nozzle is captured. Parameters are used for controlling the imaging operation. The parameters include descent start timing when each of the suction nozzles starts descent during mounting of an electronic component, and data required for determining an imaging time necessary from when a camera starts imaging of the suction nozzle until the camera ends the imaging. Imaging is completed immediately before the one suction nozzle starts descent at the work position.Type: GrantFiled: March 24, 2016Date of Patent: October 6, 2020Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Kota Ito, Junya Matsuno
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Patent number: 10431266Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.Type: GrantFiled: August 6, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: Kazuyoshi Muraoka, Masami Masuda, Junya Matsuno, Masatoshi Kohno, Yuui Shimizu
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Patent number: 10340857Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.Type: GrantFiled: September 8, 2017Date of Patent: July 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junya Matsuno, Kazuyoshi Muraoka, Masami Masuda, Yuui Shimizu, Masatoshi Kohno, Masahiro Hosoya
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Publication number: 20190116699Abstract: After one suction nozzle turns from one arrangement pitch ahead of a work position toward the work position and immediately before the suction nozzle starts descent at the work position, an image of a side portion of the suction nozzle is captured. Parameters are used for controlling the imaging operation. The parameters include descent start timing when each of the suction nozzles starts descent during mounting of an electronic component, and data required for determining an imaging time necessary from when a camera starts imaging of the suction nozzle until the camera ends the imaging. Imaging is completed immediately before the one suction nozzle starts descent at the work position.Type: ApplicationFiled: March 24, 2016Publication date: April 18, 2019Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Kota ITO, Junya MATSUNO