Patents by Inventor Junya Matsuno
Junya Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150130647Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.Type: ApplicationFiled: November 11, 2014Publication date: May 14, 2015Inventors: Tetsuro ITAKURA, Masanori FURUTA, Akihide SAI, Junya MATSUNO, Yohei HATAKEYAMA
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Publication number: 20140361917Abstract: The first amplifier operates according a first clock, changes voltages of a first terminal and a second terminal from a first fixed voltage to a second fixed voltage according to a voltage of an input signal and a first reference voltage, respectively, when an on period of a first clock starts, and keeps the voltages of the first and second terminals at the second fixed voltage, respectively, after the voltages of the first and second terminals reach the second fixed voltage and until the on period of the first clock ends, and the first comparator generates first and second logic signals that have logical levels different from each other, based on a difference between the voltages of the first and second terminals when the on period of a second clock whose on period at least partially overlaps with that of the first clock starts.Type: ApplicationFiled: June 5, 2014Publication date: December 11, 2014Inventors: Junya MATSUNO, Masanori FURUTA, Tetsuro ITAKURA
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Patent number: 8831153Abstract: According to one embodiment, a quadrature error compensating circuit for acquiring an in-phase component signal and a quadrature component signal, includes a first filter, a first multiplier, a first subtractor, a second filter, a correlation calculating circuit. The first multiplier multiplies the in-phase component signal by a control value. The correlation calculating circuit calculates a cross-correlation value between an output of the first filter and an output of the second filter, and uses the cross-correlation value as the control value.Type: GrantFiled: December 21, 2012Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Okuni, Junya Matsuno, Hideo Kasami, Tsuyoshi Kogawa
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Patent number: 8723713Abstract: There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2^n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.Type: GrantFiled: December 17, 2012Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junya Matsuno, Tetsuro Itakura
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Patent number: 8674861Abstract: An embodied ADC includes a sampling unit sampling differential input signal to output differential sampled signal which has first and second sampled signals. The ADC includes a reference signal generator generating first and second reference signals and a preamplifier amplifying the differential sampled signal to output a differential amplification signal having first and second amplified outputs. The preamplifier has a first differential amplifier amplifying the first sampled signal using the first reference signal and a second differential amplifier amplifying the second sampled signal using the second reference signal. The ADC includes a comparator comparing the first and second amplified outputs and a correction controller controlling common-mode voltage levels of the first and second reference signals or common-mode voltage levels of the first and second sampled signals in accordance with the operations of the first and second differential amplifiers.Type: GrantFiled: November 20, 2012Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junya Matsuno, Tetsuro Itakura
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Patent number: 8659454Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.Type: GrantFiled: March 20, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiko Sugimoto, Takafumi Yamaji, Junya Matsuno, Masanori Furuta
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Publication number: 20140045444Abstract: According to some embodiments, there is provided a signal sampling circuit in which the first sampling capacitor is connected to the first sampling switch, the second sampling capacitor is connected to the second sampling switch, the amplifier outputs a positive-side amplified signal by amplifying a signal input to the positive-side input terminal thereof and outputs a negative-side amplified signal by amplifying a signal input to the negative-side input terminal thereof, the first chopper switch is connected to the first sampling capacitor and the positive-side input terminal, the second chopper switch is connected to the first sampling capacitor and the negative-side input terminal, the third chopper switch is connected to the second sampling capacitor and the positive-side input terminal and the fourth chopper switch is connected to the second sampling capacitor and the negative-side input terminal.Type: ApplicationFiled: August 7, 2013Publication date: February 13, 2014Inventors: Masanori FURUTA, Junya MATSUNO
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Publication number: 20130243129Abstract: According to one embodiment, a quadrature error compensating circuit for acquiring an in-phase component signal and a quadrature component signal, includes a first filter, a first multiplier, a first subtractor, a second filter, a correlation calculating circuit. The first multiplier multiplies the in-phase component signal by a control value. The correlation calculating circuit calculates a cross-correlation value between an output of the first filter and an output of the second filter, and uses the cross-correlation value as the control value.Type: ApplicationFiled: December 21, 2012Publication date: September 19, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidenori OKUNI, Junya MATSUNO, Hideo KASAMI, Tsuyoshi KOGAWA
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Patent number: 8537039Abstract: There is provided a distortion correcting device in which a first A/D converter A/D converts a first input signal to obtain a first converted signal, a second A/D converter A/D converts a second input signal to obtain a second converted signal wherein the second input signal is a signal obtained by reducing an amplitude of the first input signal, or the first input signal is a signal obtained by increasing an amplitude of the second input signal, the exponentiator obtains an exponential signal by raising the second converted signal to an n-th power (“n” is an integer of 2 or more), a adaptive correlation controller carries out adaptive correlation control based on the exponential signal and the second converted signal to generate a distortion signal that is an n-th power component contained in the exponential signal, and a distortion remover removes the distortion signal from the first converted signal.Type: GrantFiled: March 1, 2012Date of Patent: September 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junya Matsuno, Tetsuro Itakura
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Publication number: 20130229294Abstract: An embodied ADC includes a sampling unit sampling differential input signal to output differential sampled signal which has first and second sampled signals. The ADC includes a reference signal generator generating first and second reference signals and a preamplifier amplifying the differential sampled signal to output a differential amplification signal having first and second amplified outputs. The preamplifier has a first differential amplifier amplifying the first sampled signal using the first reference signal and a second differential amplifier amplifying the second sampled signal using the second reference signal. The ADC includes a comparator comparing the first and second amplified outputs and a correction controller controlling common-mode voltage levels of the first and second reference signals or common-mode voltage levels of the first and second sampled signals in accordance with the operations of the first and second differential amplifiers.Type: ApplicationFiled: November 20, 2012Publication date: September 5, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junya MATSUNO, Tetsuro ITAKURA
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Publication number: 20130201048Abstract: There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2?n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.Type: ApplicationFiled: December 17, 2012Publication date: August 8, 2013Applicant: KABUSHKI KAISHA TOSHIBAInventors: Junya MATSUNO, Tetsuro ITAKURA
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Patent number: 8502712Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.Type: GrantFiled: March 20, 2012Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Waki, Junya Matsuno, Takafumi Yamaji, Masanori Furuta
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Publication number: 20130076545Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.Type: ApplicationFiled: March 20, 2012Publication date: March 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomohiko Sugimoto, Takafumi Yamaji, Junya Matsuno, Masanori Furuta
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Publication number: 20130076544Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.Type: ApplicationFiled: March 20, 2012Publication date: March 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoya Waki, Junya Matsuno, Takafumi Yamaji, Masanori Furuta
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Publication number: 20130044016Abstract: There is provided a distortion correcting device in which a first A/D converter A/D converts a first input signal to obtain a first converted signal, a second A/D converter A/D converts a second input signal to obtain a second converted signal wherein the second input signal is a signal obtained by reducing an amplitude of the first input signal, or the first input signal is a signal obtained by increasing an amplitude of the second input signal, the exponentiator obtains an exponential signal by raising the second converted signal to an n-th power (“n” is an integer of 2 or more), a adaptive correlation controller carries out adaptive correlation control based on the exponential signal and the second converted signal to generate a distortion signal that is an n-th power component contained in the exponential signal, and a distortion remover removes the distortion signal from the first converted signal.Type: ApplicationFiled: March 1, 2012Publication date: February 21, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junya MATSUNO, Tetsuro ITAKURA
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Publication number: 20100233986Abstract: A receiver includes a high-frequency filter which extracts, from a radio signal, a high-frequency signal, a first frequency converter which performs frequency conversion on the high-frequency signal using a first local signal, to obtain a first baseband signal, a second frequency converter which performs frequency conversion on the high-frequency signal using a second local signal, to obtain a second baseband signal, the second local signal having a frequency equal to an integral multiple of a frequency of the first local signal, and a subtraction processing unit configured to multiply the second baseband signal by a control coefficient for amplitude adjustment to obtain a product signal, and subtract the product signal from the first baseband signal to obtain a residual signal.Type: ApplicationFiled: October 15, 2009Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takafumi Yamaji, Junya Matsuno, Hiromitsu Aoyama
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Publication number: 20100112971Abstract: A receiver includes a multiphase mixer that multiplies a received radio signal by multiphase local signals the number of which is the same as an integer having a first prime factor and a second prime factor different from the first prime factor, and generates first multiphase baseband signals the number of which is the same as the integer, a first processing circuit that suppresses common modes for first multiphase signal groups formed by dividing the first multiphase baseband signals into groups of signals the number of which is the same as the first prime factor, and generates second multiphase baseband signals, and a second processing circuit that suppresses common modes for second multiphase signal groups formed by dividing the second multiphase baseband signals into groups of signals the number of which is the same as the second prime factor, and generates third multiphase baseband signals.Type: ApplicationFiled: July 15, 2009Publication date: May 6, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junya Matsuno, Takafumi Yamaji, Tetsuro Itakura