Patents by Inventor Junya Narita
Junya Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079517Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: NICHIA CORPORATIONInventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
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Patent number: 11855238Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.Type: GrantFiled: June 3, 2021Date of Patent: December 26, 2023Assignee: NICHIA CORPORATIONInventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
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Patent number: 11508701Abstract: Each of a plurality of light emitting elements has a hexagonal shape with a center. An interior angle at each of corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first lateral side surface and a second light emitting element having a second lateral side surface. An orientation of the hexagonal shape of the second light emitting element is rotated by 30 degrees plus 30°+60°×N (N is an integer) with respect to the center of the second light emitting element relative to an orientation of the hexagonal shape of the first light emitting element such that the second lateral side surface is not parallel to the first lateral side surface.Type: GrantFiled: June 10, 2020Date of Patent: November 22, 2022Assignee: NICHIA CORPORATIONInventors: Masaki Hayashi, Yuki Shiota, Junya Narita, Keisuke Kurashita, Takanori Akaishi
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Publication number: 20210296526Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Applicant: NICHIA CORPORATIONInventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
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Patent number: 11056612Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.Type: GrantFiled: November 7, 2019Date of Patent: July 6, 2021Assignee: NICHIA CORPORATIONInventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
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Publication number: 20200303357Abstract: Each of a plurality of light emitting elements has a hexagonal shape with a center. An interior angle at each of corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first lateral side surface and a second light emitting element having a second lateral side surface. An orientation of the hexagonal shape of the second light emitting element is rotated by 30 degrees plus 30°+60°×N (N is an integer) with respect to the center of the second light emitting element relative to an orientation of the hexagonal shape of the first light emitting element such that the second lateral side surface is not parallel to the first lateral side surface.Type: ApplicationFiled: June 10, 2020Publication date: September 24, 2020Applicant: NICHIA CORPORATIONInventors: Masaki HAYASHI, Yuki SHIOTA, Junya NARITA, Keisuke KURASHITA, Takanori AKAISHI
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Patent number: 10720412Abstract: Each of a plurality of light emitting elements has a polygonal shape with five or more corners. An interior angle at each of the corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first bottom surface, a first top surface opposite to the first bottom surface, and a first lateral side surface between the first bottom surface and the first top surface. The second light emitting element has a second bottom surface, a second top surface opposite to the second bottom surface, and a second lateral side surface between the second bottom surface and the second top surface. The second lateral side surface is provided not to oppose to the first lateral side surface in substantially parallel.Type: GrantFiled: February 12, 2016Date of Patent: July 21, 2020Assignee: NICHIA CORPORATIONInventors: Masaki Hayashi, Yuki Shiota, Junya Narita, Keisuke Kurashita, Takanori Akaishi
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Publication number: 20200075797Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Applicant: NICHIA CORPORATIONInventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
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Patent number: 10505072Abstract: A method for manufacturing a plurality of light emitting elements includes: providing a semiconductor wafer comprising: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer; forming a protective layer on an upper face of the p-side nitride semiconductor layer in regions that include borders of areas to become the plurality of light emitting elements; reducing a resistance of the p-side nitride semiconductor in areas where no protective layer has been formed by annealing the semiconductor wafer; irradiating a laser beam on the substrate so as to form modified regions in the substrate; and obtaining a plurality of light emitting elements by dividing the semiconductor wafer in which the modified regions have been formed in the substrate.Type: GrantFiled: December 14, 2017Date of Patent: December 10, 2019Assignee: NICHIA CORPORATIONInventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
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Patent number: 10490694Abstract: A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.Type: GrantFiled: March 30, 2018Date of Patent: November 26, 2019Assignee: NICHIA CORPORATIONInventors: Kazuhiro Nagamine, Yoshiki Inoue, Susumu Toko, Junya Narita
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Patent number: 10388827Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.Type: GrantFiled: October 2, 2018Date of Patent: August 20, 2019Assignee: NICHIA CORPORATIONInventors: Hiroki Okamoto, Hiroaki Tamemoto, Junya Narita
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Publication number: 20190035973Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Applicant: NICHIA CORPORATIONInventors: Hiroki OKAMOTO, Hiroaki TAMEMOTO, Junya NARITA
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Patent number: 10115857Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.Type: GrantFiled: June 29, 2016Date of Patent: October 30, 2018Assignee: NICHIA CORPORATIONInventors: Hiroki Okamoto, Hiroaki Tamemoto, Junya Narita
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Publication number: 20180287009Abstract: A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.Type: ApplicationFiled: March 30, 2018Publication date: October 4, 2018Applicant: NICHIA CORPORATIONInventors: Kazuhiro NAGAMINE, Yoshiki INOUE, Susumu TOKO, Junya NARITA
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Publication number: 20180175238Abstract: A method for manufacturing a plurality of light emitting elements includes: providing a semiconductor wafer comprising: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer; forming a protective layer on an upper face of the p-side nitride semiconductor layer in regions that include borders of areas to become the plurality of light emitting elements; reducing a resistance of the p-side nitride semiconductor in areas where no protective layer has been formed by annealing the semiconductor wafer; irradiating a laser beam on the substrate so as to form modified regions in the substrate; and obtaining a plurality of light emitting elements by dividing the semiconductor wafer in which the modified regions have been formed in the substrate.Type: ApplicationFiled: December 14, 2017Publication date: June 21, 2018Applicant: NICHIA CORPORATIONInventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
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Patent number: 9873170Abstract: A method of manufacturing a light emitting element includes providing a wafer having a substrate and a semiconductor layered body provided on an upper surface of the substrate, irradiating the substrate with laser light from a side of a lower surface opposite to the upper surface of the substrate to form modified regions in the substrate, and dividing the wafer into light emitting elements at the modified regions as a starting point. The semiconductor layered body includes a first p-type semiconductor layer made of a nitride semiconductor and provided on the upper surface of the substrate, an n-type semiconductor layer made of a nitride semiconductor and provided on the first p-type semiconductor layer, an active layer made of a nitride semiconductor and provided on the n-type semiconductor layer, and a second p-type semiconductor layer made of a nitride semiconductor and provided on the active layer.Type: GrantFiled: March 24, 2016Date of Patent: January 23, 2018Assignee: NICHIA CORPORATIONInventors: Junya Narita, Takuya Okada
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Patent number: 9761764Abstract: A light emitting device includes a package and at least one light emitting element. The package includes a recess portion which has a bottom surface, an opening on a front side opposite to the bottom surface in a front direction vertical to the bottom surface, and an inner peripheral wall connecting the bottom surface and the front side. The bottom surface has distances between opposite sides of the bottom surface and has a longest distance among the distances. The at least one light emitting element is disposed on the bottom surface of the recess portion and has a polygonal shape which has five or more sides and which has a longest diagonal line viewed along the front direction. Each internal angle of the polygonal shape is less than 180°. The longest diagonal line of the polygonal shape is parallel to a lateral line along the longest distance.Type: GrantFiled: January 25, 2016Date of Patent: September 12, 2017Assignee: NICHIA CORPORATIONInventors: Masaki Hayashi, Yuki Shiota, Junya Narita, Keisuke Kurashita, Takanori Akaishi, Motohisa Kitani
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Patent number: 9559253Abstract: A method of manufacturing a nitride semiconductor element includes preparing a wafer having a nitride semiconductor layer which includes p-type dopants, forming an altered portion by condensing laser beam on the wafer, and after the forming an altered portion, forming a p-type nitride semiconductor layer by subjecting the wafer to annealing.Type: GrantFiled: October 29, 2014Date of Patent: January 31, 2017Assignee: NICHIA CORPORATIONInventors: Junya Narita, Yohei Wakai, Kazuto Okamoto, Mizuki Nishioka
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Publication number: 20170005225Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.Type: ApplicationFiled: June 29, 2016Publication date: January 5, 2017Applicant: NICHIA CORPORATIONInventors: Hiroki OKAMOTO, Hiroaki TAMEMOTO, Junya NARITA
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Patent number: 9525103Abstract: The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections.Type: GrantFiled: June 9, 2015Date of Patent: December 20, 2016Assignee: NICHIA CORPORATIONInventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan