Abstract: A portable communication device or electronic device is provided. The communication device includes a housing including a first housing structure, a second housing structure, and a hinge cover positioned between at least a portion of the first housing structure and at least a portion of the second housing structure, a flexible display at least partially received in the housing and including a first portion corresponding to the first housing structure, a second portion corresponding to the second housing structure, and a third portion corresponding to the hinge cover, a hinge structure positioned between the third portion of the flexible display and the hinge cover and connected with the first housing structure and the second housing structure, and at least one sealing member positioned between the third portion of the flexible display and the hinge cover and contacting the hinge cover.

Abstract: A portable communication device or electronic device is provided. The communication device includes a housing including a first housing structure, a second housing structure, and a hinge cover positioned between at least a portion of the first housing structure and at least a portion of the second housing structure, a flexible display at least partially received in the housing and including a first portion corresponding to the first housing structure, a second portion corresponding to the second housing structure, and a third portion corresponding to the hinge cover, a hinge structure positioned between the third portion of the flexible display and the hinge cover and connected with the first housing structure and the second housing structure, and at least one sealing member positioned between the third portion of the flexible display and the hinge cover and contacting the hinge cover.

Abstract: A semiconductor chip stack structure includes: a first semiconductor chip including a first semiconductor substrate, a first redistribution layer on the first semiconductor substrate and including a first redistribution pattern, and a first pad on an outermost side of the first redistribution layer; a second semiconductor chip including a second semiconductor substrate, a second redistribution layer on the second semiconductor substrate and including a second redistribution pattern, and a second pad on an outermost side of the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire on the first semiconductor chip; a second metal wire on the second semiconductor chip; and a molding member on the first semiconductor chip and at least a portion of each of the second semiconductor chip, the first metal wire, and the second metal wire.

Abstract: According to various embodiments, an electronic device may include a communication circuit operably coupled with an external electronic device and at least one processor, wherein the at least one processor may be configured to determine one or more target-wake-time (TWT) parameters of at least one TWT service period based on at least one of the amount of data transmitted to the external electronic device, an amount of data received from the external electronic device, or a bandwidth, wherein at least one data frame is transmitted or received between the electronic device and the external electronic device during the at least one TWT service period; identify quality of service (QoS) for the at least one data frame transmitted or received during the at least one TWT service period; change at least one TWT parameter among the one or more TWT parameters based on the identified QoS; and control the communication circuit to transmit or receive at least one next data frame during the a next TWT service period based

Abstract: A display apparatus includes a substrate, a display unit, a wire structure, and a first power supply structure. The substrate includes a display area, a first non-display area neighboring the display area, a second non-display area, and a bending area between the first non-display area and the second non-display area. The display unit is on the display area. The wire structure is on the first non-display area, the bending area, and the second non-display area and includes a first wire set and a second wire set overlapping the bending area and spaced from each other. The first power supply structure includes a first conductive line and a second conductive line on the first non-display area and the second non-display area, respectively, and includes a connection line connecting the first conductive line to the second conductive line and positioned between the first wire set and the second wire set. optimized.

Abstract: A semiconductor package includes a substrate including a first region, a second region in contact with the first region with the first and second regions stacked in a first direction, and a third region extending from the first and second regions in a second direction, perpendicular to the first direction, to connect the first and second regions to each other in bent form, a first semiconductor chip on a first side opposite to a second side of the first region in contact with the second region, a second semiconductor chip on a first side opposite to a second side of the second region in contact with the first region, a first molding member on the first region and covering at least a portion of the first semiconductor chip, and a second molding member on the second region and covering at least a portion of the second semiconductor chip.

Abstract: An electronic device includes a system on-chip that outputs a write clock and a write data signal, and a memory device that receives the write data signal based on the write clock and outputs a read data signal and a data strobe signal whose frequency is different from a frequency of the write clock. The memory device further includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs a first training in initialization of the electronic device and performs a second training in an operation after the initialization. The memory device performs a counting operation during an operation of an interval oscillator in the second training and corrects a final count value with reference to temperature information of the memory device.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

Abstract: The present disclosure relates to a clothes treatment apparatus comprising: an outer case having a first opening of which the front is open; an inner case provided inside the outer case; a machine room forming part positioned at the lower part of the inner case so as to form a machine room separated from the inner case; a foaming space formed between the outer case and the machine room forming part; foamed plastics filled in the foaming space; and strength reinforcing parts positioned at both side surfaces of the outer case in the foaming space so as to reinforce the strength of the outer case.

Abstract: A memory control device includes a threshold generating circuit, which is configured to set a first threshold for a first memory module electrically coupled to the memory control device. This first threshold is based on information associated with the first memory module. An attack defense circuit is also provided, which is configured to count an input row address, and decide a row address whose count value exceeds the first threshold among row addresses of the first memory module as an aggressor row address.

Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Abstract: An electronic device is provided.

Abstract: A method and an apparatus for controlling communication parameters in multiple communication are provided. The apparatus includes a memory and a processor operatively coupled to the memory, wherein the memory includes instructions for allowing the processor to, set a first service period duration and a first wake interval, related to first communication, on the basis of the quality of service of the first communication, set a second service period duration and a second wake interval, related to second communication, on the basis of the quality of service of the second communication when a second communication connection having a frequency overlapping with that of the first communication is detected, determine whether the time difference between the first wake interval and the second wake interval occurs, and change, on the basis of the determination result, the first wake interval and the second wake interval to correspond to each other.

Abstract: Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.

Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: An electronic device is disclosed herein.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.