Patents by Inventor Justin K. Brask

Justin K. Brask has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8368135
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Metal gate transistors with raised source and drain regions formed on heavily doped substrate
    Patent number: 8344452
    Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Justin K. Brask, Andrew Westmeyer
  • CMOS devices with a single work function gate electrode and method of fabrication
    Patent number: 8294180
    Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Justin K. Brask, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20120205729
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • EXTREME HIGH MOBILITY CMOS LOGIC
    Publication number: 20120199813
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Applicant: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
    Patent number: 8193567
    Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8183646
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Extreme high mobility CMOS logic
    Patent number: 8183556
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Suman Datt{dot over (a)}, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amlan, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Patent number: 8148786
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau
  • Inducing strain in the channels of metal gate transistors
    Patent number: 8129795
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 8119508
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Tensile strained NMOS transistor using group III-N source/drain regions
    Patent number: 8120065
    Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Been-Yih Jin, Jack T. Kavalieros, Mantu K. Hudait
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20120032237
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION
    Publication number: 20120012934
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Semiconductor device structures and methods of forming semiconductor structures
    Patent number: 8071983
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 6, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 8067818
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Dielectric interface for group III-V semiconductor device
    Patent number: 7989280
    Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
  • CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION
    Publication number: 20110180851
    Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
    Type: Application
    Filed: March 1, 2011
    Publication date: July 28, 2011
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Justin K. Brask, Robert S. Chau
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20110156174
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR
    Publication number: 20110156145
    Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian S. Doyle, Justin K. Brask, Robert S. Chau