Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

Abstract: The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.

Abstract: A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.

Abstract: The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.

Abstract: A radio frequency circuit for summing signals from multiple lobes of an antenna includes circuitry for converting RF signals from lobes of an antenna to baseband signals, and circuitry for summing the baseband signals from the lobes of an antenna.

Abstract: Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.

Abstract: Systems with semiconductor devices that are DC-biased at either their weak inversion (i.e., sub-threshold) region or their strong inversion region. In a preferred embodiment using semiconductor devices (e.g., NMOS, PMOS, etc.), a gate to source voltage (Vgs) is slightly below the threshold voltage (Vtn) of the device. These weakly turned-on semiconductor devices increase the receiving AC sensitivity of an AM-Detector compared to that of a conventional AM-Detector without any DC-biasing. Further, the compensating bias voltage (Vbias) compensates for one or both of the ambient temperature change and the foundry's process variation of the various semiconductor devices.

Abstract: a circuit for an RFID device in one embodiment includes an operational amplifier having a first input, a second input, and an output where the first input receives an incoming signal, arid the second input is coupled to the output via a feedback loop. An operational amplifier for an RFID device according to another embodiment compares an output of the operational amplifier to an incoming baseband signal, A circuit according to another embodiment includes an operational amplifier having a first input, a second input, and an output, wherein the first input receives an incoming signal, and wherein the second input is coupled to the output via a feedback loop. A comparator having one input is coupled to the output of the operational amplifier, another input receiving the incoming signal, and an output for outputting an outgoing signal. Methods for adjusting a filtering characteristic of an operational amplifier are also disclosed.

Abstract: a circuit for an RFID device in one embodiment includes an operational amplifier having a first input, a second input, and an output where the first input receives an incoming signal, arid the second input is coupled to the output via a feedback loop. An operational amplifier for an RFID device according to another embodiment compares an output of the operational amplifier to an incoming baseband signal, A circuit according to another embodiment includes an operational amplifier having a first input, a second input, and an output, wherein the first input receives an incoming signal, and wherein the second input is coupled to the output via a feedback loop. A comparator having one input is coupled to the output of the operational amplifier, another input receiving the incoming signal, and an output for outputting an outgoing signal. Methods for adjusting a filtering characteristic of an operational amplifier are also disclosed.

Abstract: Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.

Abstract: A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.

Abstract: A circuit according to one embodiment of the present invention includes a first frequency to voltage converter for storing a reference voltage based on a frequency of an incoming signal, and a second frequency to voltage converter for storing a second voltage based on the frequency of the incoming signal, the second voltage being a fraction of the reference voltage. A voltage to frequency converter creates a voltage on a node, the voltage repeatedly varying between about the reference voltage and about the second voltage. From this varying signal, a clock signal can be derived.

Abstract: Systems with semiconductor devices that are DC-biased at either their weak inversion (i.e., sub-threshold) region or their strong inversion region. In a preferred embodiment using semiconductor devices (e.g., NMOS, PMOS, etc.), a gate to source voltage (Vgs) is slightly below the threshold voltage (Vtn) of the device. These weakly turned-on semiconductor devices increase the receiving AC sensitivity of an AM-Detector compared to that of a conventional AM-Detector without any DC-biasing. Further, the compensating bias voltage (Vbias) compensates for one or both of the ambient temperature change and the foundry's process variation of the various semiconductor devices.

Abstract: A radio frequency (RF) system having omnidirectional functionality, such that the antenna is functional in a generally isotropic manner. The system in one embodiment includes a supporting substrate, a circuit coupled to the substrate, and an antenna coupled to the circuit, the antenna having multiple lobes, wherein responses from the lobes are demodulated and combined at baseband. The circuit can be positioned over a physical area of a portion of the antenna, the antenna acting as a virtual ground plane for the circuit.

Abstract: A radio frequency (RF) system having omindirectional functionality includes a supporting substrate, a circuit coupled to the substrate, and an antenna coupled to the circuit, the antenna having multiple lobes, wherein responses from the lobes are demodulated and combined at baseband. The circuit is positioned over a physical area of a portion of the antenna, the antenna acting as a virtual ground plane for the circuit.

Abstract: A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.

Abstract: A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time.

Abstract: A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time.