Abstract: A loop filter circuit in a phase lock loop, which also includes a phase detector, a charge pump, and a voltage controlled oscillator (VCO). The loop filter circuit is comprised of two active filters and a common mode feedback control differential comparator (CMFCDC). The active filters process differential signals from the charge pump and output a pair of differential signals to the VCO. The CMFCDC provides a common mode feedback path to both active filters. The loop filter circuit eliminates common mode noise introduced by power supply and ground, and reduces phase jitter in the overall PLL circuits. Each of the active filters is comprised of two independent sets of passive elements that dictate the values of natural modes (poles) and transmission zeros (zeros) of the filtering modules. This allows PLL designers wider latitude in adjusting the unity gain bandwidth of the active loop filter, which contributes to a more stable and better performing PLL circuit.

Abstract: Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder.

Abstract: A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.

Abstract: Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance.

Abstract: A logic converter enables a digital logic product to work with either an ECL signal input or a TTL signal input without any need of modifying or reconfiguring the product. In particular, the logic converter converts digital input signals of a first logic type (for example, ECL) to digital output signals of a third logic type (for example, CMOS). It also converts digital input signals of a second logic type (for example, TTL) to digital output signals of the third logic type. A first operational transconductance amplifier circuit including a first differential amplifier using a differential transistor pair of a first conduction type receives digital input signals of the first logic type and converts the digital input signals to digital output signals of the third logic type.

Abstract: An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device.