Patents by Inventor Kai-Chih Liang

Kai-Chih Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140015069
    Abstract: MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Chun-Wen Cheng
  • Publication number: 20130168852
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Application
    Filed: August 9, 2012
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Publication number: 20130105868
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Application
    Filed: May 24, 2012
    Publication date: May 2, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 8368152
    Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Yi Heng Tsai, Kai-Chih Liang, Chia-Pao Shu, Li-Cheng Chu, Kuei-Sung Chang, Hsueh-An Yang, Chung-Hsien Lin
  • Publication number: 20120261830
    Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 18, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua Chu, Yi Heng Tsai, Kai-Chih Liang, Chia-Pao Shu, Li-Cheng Chu, Kuei-Sung Chang, Hsueh-An Yang, Chung-Hsien Lin
  • Publication number: 20120091454
    Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Wen-Chuan Tai, Chun-Ren Cheng
  • Patent number: 8012785
    Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y. M. Shen, Allen Timothy Chang
  • Publication number: 20100273286
    Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y.M. Shen, Allen Timothy Chang
  • Patent number: 7732299
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 8, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiang Ho, Gwo-Yuh Shiau, Chu-Wei Cheng, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai
  • Publication number: 20080194076
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 14, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiung Ho, Gwo-Yuh Shiau, Chu-Wei Chang, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai