Patents by Inventor Kai Esmark

Kai Esmark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050001270
    Abstract: A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.
    Type: Application
    Filed: July 29, 2004
    Publication date: January 6, 2005
    Inventors: Kai Esmark, Harald Gossner, Gunther Mackh, Richard Owen, Franz Zangl
  • Publication number: 20050003564
    Abstract: A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
    Type: Application
    Filed: June 14, 2004
    Publication date: January 6, 2005
    Inventors: Silke Bargstadt-Franke, Kai Esmark, Harald Gossner, Philipp Riess, Wolfgang Stadler, Martin Streibl, Martin Wendel
  • Publication number: 20030064573
    Abstract: A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 3, 2003
    Inventors: Kai Esmark, Harald Gossner, Gunther Mackh, Richard Owen, Franz Zangl
  • Publication number: 20030017676
    Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).
    Type: Application
    Filed: July 19, 2002
    Publication date: January 23, 2003
    Inventors: Kai Esmark, Harald Gossner, Philipp Riess, Wolfgang Stadler, Martin Streibl, Martin Wendel
  • Publication number: 20030006776
    Abstract: To test the ESD resistance of a semiconductor component (1), for example of a NOS transistor, which can be used as an PSD protective element in a chip (2), a direct current characteristic of the semiconductor component (1) is monitored and the ESD resistance of the respective semiconductor component (1) is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component (1) at which an increased leakage current occurs in the non-conducting direction of the semiconductor component (1) can be monitored in operation of the semiconductor coponent (1) using an applied direct current (Io) and the ESD resistance of the semiconductor component (1) inferred depending on a change in this direct current failure threshold.
    Type: Application
    Filed: May 31, 2002
    Publication date: January 9, 2003
    Applicant: Infineon Technologies AG, Germany
    Inventors: Martin Wendel, Richard Owen, Harald Gossner, Wolfgang Stadler, Philipp Riess, Martin Streibl, Kai Esmark