Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

Abstract: A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed. on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.

Abstract: A light-emitting diode package includes a redistribution layer, a light-emitting diode, a first dielectric layer, a plurality of wavelength conversion structures, and a transparent encapsulant. The light-emitting diode is disposed on and electrically connected to the redistribution layer. The light-emitting diode includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first dielectric layer is disposed on the redistribution layer and covers the light-emitting diode. The wavelength conversion structures are disposed on the first dielectric layer and respectively in contact with the second light-emitting diode and the third light-emitting diode. The transparent encapsulant is disposed on the first dielectric layer and covers the plurality of wavelength conversion structures. In addition, a manufacturing method of the light-emitting diode package is provided.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

Abstract: A method for forming resistance on circuit board is provided and includes the following steps. First, a substrate is provided. Next, a second metal layer is provided on the substrate, and the first metal layer is covered by the second metal layer. Then, a resistance is formed on the second metal layer, and the resistance is directly above the first metal layer. Thereafter, the second metal layer is cut so that the edge of the second metal layer is aligned with that of the first metal layer. The second metal layer is separated from the first metal layer. Next, the second metal layer is pressed with a circuit board, and the resistance is attached to a dielectric layer of the circuit board. Then, the second metal layer is etched to form a circuit pattern on the resistance.

Abstract: A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.

Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.