Patents by Inventor Kai-Ming Yang

Kai-Ming Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200367364
    Abstract: A circuit board including a substrate, a patterned conductive layer, a patterned insulating layer, a conductive terminal, and a dummy terminal is provided. The patterned conductive layer is disposed on the substrate. The patterned insulating layer is disposed on the substrate and at least covers a portion of the patterned conductive layer. The conductive terminal is disposed on the patterned conductive layer and has a first top surface. The dummy terminal is disposed on the patterned conductive layer and has a second top surface. A first height between the first top surface and the substrate is greater than a second height between the second top surface and the substrate.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 19, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Patent number: 10756050
    Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package structure is also provided.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 25, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen
  • Patent number: 10658282
    Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen, Tzyy-Jang Tseng
  • Publication number: 20200154578
    Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 14, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Patent number: 10588214
    Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.
    Type: Grant
    Filed: August 18, 2019
    Date of Patent: March 10, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzyy-Jang Tseng, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen
  • Publication number: 20200068721
    Abstract: A package structure, includes a metal layer, an insulating composite layer disposed thereon, a sealant bonded on the insulating composite layer, a chip embedded in the sealant, a circuit layer structure disposed on the sealant and the chip, and a protecting layer. The chip has a plurality of electrode pads exposed from the sealant. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind vias. The dielectric layer and the sealant are made of the same material. The circuit layer is disposed on the dielectric layer and extends into the conductive blind vias, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind vias. The protecting layer is formed on the circuit layer structure and has a plurality of openings exposing a portion of the circuit layer structure.
    Type: Application
    Filed: November 3, 2019
    Publication date: February 27, 2020
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Wang-Hsiang TSAI, Cheng-Ta KO
  • Publication number: 20200043890
    Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package structure is also provided.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 6, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen
  • Publication number: 20200043839
    Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 6, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen, Tzyy-Jang Tseng
  • Publication number: 20190373713
    Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.
    Type: Application
    Filed: August 18, 2019
    Publication date: December 5, 2019
    Inventors: Tzyy-Jang TSENG, Kai-Ming YANG, Pu-Ju LIN, Cheng-Ta KO, Yu-Hua CHEN
  • Publication number: 20190306987
    Abstract: A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 3, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Kai-Ming Yang, Chih-Lun Wang
  • Publication number: 20190239362
    Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Cheng-Ta KO, John Hon-Shing LAU, Yu-Hua CHEN, Tzyy-Jang TSENG
  • Publication number: 20190098746
    Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Ra-Min TAIN, Kai-Ming YANG, Chien-Tsai LI
  • Patent number: 10178755
    Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 8, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ra-Min Tain, Kai-Ming Yang, Chien-Tsai Li
  • Publication number: 20180332700
    Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Inventors: Ra-Min TAIN, Kai-Ming YANG, Chien-Tsai LI
  • Patent number: 9906715
    Abstract: An electronic device includes a first camera module photographing according to a first frame rate, a second camera module photographing according to a second frame rate and a multimedia processor coupled to the first camera module and the second camera module. The multimedia processor instructs the first camera module and the second camera module to alternately photograph to obtain a sequence of pictures recorded at a third frame rate. The third frame rate is higher than the first frame rate and the second frame rate.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: February 27, 2018
    Assignee: HTC CORPORATION
    Inventor: Kai-Ming Yang
  • Publication number: 20170374748
    Abstract: A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Wang-Hsiang TSAI, Cheng-Ta KO
  • Publication number: 20170110393
    Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Kai-Ming Yang, Wang-Hsiang Tsai, Tzyy-Jang Tseng
  • Publication number: 20170013192
    Abstract: An electronic device includes a first camera module photographing according to a first frame rate, a second camera module photographing according to a second frame rate and a multimedia processor coupled to the first camera module and the second camera module. The multimedia processor instructs the first camera module and the second camera module to alternately photograph to obtain a sequence of pictures recorded at a third frame rate. The third frame rate is higher than the first frame rate and the second frame rate.
    Type: Application
    Filed: November 25, 2015
    Publication date: January 12, 2017
    Applicant: HTC Corporation
    Inventor: Kai-Ming YANG
  • Patent number: 8277101
    Abstract: An LED headlight cooling system includes a vehicle air conditioner, a thermal conducting device and an LED headlight. The vehicle air conditioner has a cooling device. The thermal conducting device is thermally connected to the cooling device of the vehicle air conditioner. The LED headlight is thermally connected to the thermal conducting device.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: October 2, 2012
    Inventors: Chih-Chiu Shen, Kai-Ming Yang, Kai-Jen Yang, Su-Hon Lin
  • Publication number: 20110157910
    Abstract: An LED headlight cooling system includes a vehicle air conditioner, a thermal conducting device and an LED headlight. The vehicle air conditioner has a cooling device. The thermal conducting device is thermally connected to the cooling device of the vehicle air conditioner. The LED headlight is thermally connected to the thermal conducting device.
    Type: Application
    Filed: April 21, 2010
    Publication date: June 30, 2011
    Inventors: Chih-Chiu SHEN, Kai-Ming YANG, Kai-Jen YANG, Su-Hon LIN