Patents by Inventor Kallol Chatterjee
Kallol Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9325490Abstract: A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/?0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.Type: GrantFiled: March 20, 2014Date of Patent: April 26, 2016Assignee: STMicroelectronics International N.V.Inventors: Anurag Tiwari, Kallol Chatterjee
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Patent number: 9160336Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.Type: GrantFiled: December 14, 2012Date of Patent: October 13, 2015Assignee: STMICROELECTRONICS PVT LTDInventors: Abhishek Jain, Chittoor Parthasarathy, Kallol Chatterjee
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Publication number: 20150270947Abstract: A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/?0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: STMicroelectronics International N.V.Inventors: Anurag TIWARI, Kallol CHATTERJEE
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Patent number: 9054637Abstract: An amplitude limiting circuit for a crystal oscillator circuit includes a current source configured to supply drive current to the crystal oscillator circuit and a current sensing circuit configured to sense operating current in an inverting transistor of the crystal oscillator circuit. The current comparison circuit functions to compare the sensed operating current to at least a reference current and generate an output signal. A current control circuit generates a control signal for controlling operation of the current source in response to the output signal.Type: GrantFiled: January 10, 2014Date of Patent: June 9, 2015Assignee: STMicroelectronics International N.V.Inventors: Gauri Mittal, Kallol Chatterjee
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Patent number: 9021324Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.Type: GrantFiled: December 21, 2010Date of Patent: April 28, 2015Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Kallol Chatterjee, Chittoor Parthasarathy
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Patent number: 8994416Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: GrantFiled: October 3, 2013Date of Patent: March 31, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Chittoor Parthasarathy, Nitin Chawla, Kallol Chatterjee, Pascal Urard
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Patent number: 8981817Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.Type: GrantFiled: June 25, 2013Date of Patent: March 17, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SASInventors: Vinod Kumar, Pradeep Kumar Badrathwal, Saiyid Mohammad Irshad Rizvi, Paras Garg, Kallol Chatterjee, Pierre Dautriche
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Patent number: 8933737Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.Type: GrantFiled: October 4, 2013Date of Patent: January 13, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SASInventors: Kallol Chatterjee, Nitin Agarwal, Junaid Yousuf, Nitin Gupta, Pierre Dautriche
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Publication number: 20150002197Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.Type: ApplicationFiled: October 4, 2013Publication date: January 1, 2015Applicants: STMicroelectronics International N.V., STMicroelectronics (CROLLES 2) SASInventors: Kallol CHATTERJEE, Nitin AGARWAL, Junaid YOUSUF, Nitin GUPTA, Pierre DAUTRICHE
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Publication number: 20150002110Abstract: A method and apparatus are provided. The apparatus comprises a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.Type: ApplicationFiled: June 27, 2013Publication date: January 1, 2015Inventors: Saurabh Kumar Singh, Nitin Bansal, Kallol Chatterjee
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Publication number: 20140375357Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Vinod KUMAR, Pradeep Kumar BADRATHWAL, Saiyid Mohammad Irshad RIZVI, Paras GARG, Kallol CHATTERJEE, Pierre DAUTRICHE
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Publication number: 20140167812Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: STMicroelectronics International N.V.Inventors: Abhishek Jain, Chittoor Parthasarathy, Kallol Chatterjee
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Patent number: 8754620Abstract: Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.Type: GrantFiled: February 2, 2010Date of Patent: June 17, 2014Assignee: STMicroelectronics International N.V.Inventors: Nitin Bansal, Kallol Chatterjee
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Publication number: 20140035644Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicants: STMicroelectronics SA, STMicroelectronics International N.V.Inventors: Chittoor PARTHASARATHY, Nitin CHAWLA, Kallol CHATTERJEE, Pascal URARD
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Patent number: 8552765Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: GrantFiled: June 30, 2011Date of Patent: October 8, 2013Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Chittoor Parthasarathy, Nitin Chawla, Kallol Chatterjee, Pascal Urard
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Patent number: 8456195Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.Type: GrantFiled: April 13, 2012Date of Patent: June 4, 2013Assignee: STMicroelectronics International N.V.Inventors: Kallol Chatterjee, Anurag Tiwari
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Publication number: 20130003905Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Abhishek JAIN, Kallol CHATTERJEE, Chittoor PARTHASARATHY, Saurabh Kumar SINGH
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Patent number: 8269545Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.Type: GrantFiled: October 31, 2011Date of Patent: September 18, 2012Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Chittoor Parthasarathy, Kallol Chatterjee, Promod Kumar
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Publication number: 20120218002Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.Type: ApplicationFiled: April 13, 2012Publication date: August 30, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Kallol Chatterjee, Anurag Tiwari
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Publication number: 20120176173Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: ApplicationFiled: June 30, 2011Publication date: July 12, 2012Applicants: STMICROELECTRONICS SA, STMicroelectronics Pvt Ltd.Inventors: Chittoor PARTHASARATHY, Nitin Chawla, Kallol Chatterjee, Pascal Urard