Abstract: A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

Abstract: An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.

Abstract: The invention relates to an improved phase locked loop (PLL) circuit for preventing erroneous condition in the charge pump operation. The invention includes modification in the PLL circuitry by adding delay elements for connection between the phase frequency detector and the charge pump and a digital logic circuit for obtaining the clock signals for the loop filter.

Abstract: A memory chip configuration aims that reduces the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of—a n×m FET matrix, vertically running bitlines—each shared by a column in the array, horizontally running wordlines—each shared by a row in the array, horizontally running sourcelines—each shared by a row in the array. The sourceline signal for a row is generated by complementing the wordline signal for the same row. The memory cell read operations with the proposed configuration, substantially control the bitline leakage current thereby enhancing the memory speed by reducing the noise during read operations. Also the configuration is unconstrained by design parameters that include size and geometries of memory chips, cell densities, complexity of memory structures, fabrication technologies, etc.

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract: A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract: An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.