Patents by Inventor Kalman Pelhos
Kalman Pelhos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220028696Abstract: A method of forming a feature in a stack comprising a dielectric material on a substrate is provided. An etch plasma is generated from an etch gas, exposing the stack to the etch plasma and partially etching the feature in the stack. The stack is primed. A protective film is deposited on sidewalls of the feature by repeating for a plurality of cycles the steps of exposing the stack to a first reactant, allowing the first reactant to adsorb onto the stack, and exposing the stack to a second reactant, wherein the first and second reactants react with one another to form the protective film over the stack. The etching, priming, and depositing a protective film are repeated until the feature is etched to a final depth.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: Eric HUDSON, Kalman PELHOS
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Patent number: 11171011Abstract: A method of forming a feature in a stack comprising a dielectric material on a substrate is provided. An etch plasma is generated from an etch gas, exposing the stack to the etch plasma and partially etching the feature in the stack. The stack is primed. A protective film is deposited on sidewalls of the feature by repeating for a plurality of cycles the steps of exposing the stack to a first reactant, allowing the first reactant to adsorb onto the stack, and exposing the stack to a second reactant, wherein the first and second reactants react with one another to form the protective film over the stack. The etching, priming, and depositing a protective film are repeated until the feature is etched to a final depth.Type: GrantFiled: August 21, 2018Date of Patent: November 9, 2021Assignee: Lam Research CorporationInventors: Eric Hudson, Kalman Pelhos
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Publication number: 20200066540Abstract: A method of forming a feature in a stack comprising a dielectric material on a substrate is provided. An etch plasma is generated from an etch gas, exposing the stack to the etch plasma and partially etching the feature in the stack. The stack is primed. A protective film is deposited on sidewalls of the feature by repeating for a plurality of cycles the steps of exposing the stack to a first reactant, allowing the first reactant to adsorb onto the stack, and exposing the stack to a second reactant, wherein the first and second reactants react with one another to form the protective film over the stack. The etching, priming, and depositing a protective film are repeated until the feature is etched to a final depth.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Eric HUDSON, Kalman PELHOS
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Patent number: 10431458Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.Type: GrantFiled: November 22, 2016Date of Patent: October 1, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
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Patent number: 10170323Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.Type: GrantFiled: February 23, 2017Date of Patent: January 1, 2019Assignee: Lam Research CorporationInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
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Publication number: 20170170026Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.Type: ApplicationFiled: February 23, 2017Publication date: June 15, 2017Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
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Patent number: 9620377Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.Type: GrantFiled: July 20, 2015Date of Patent: April 11, 2017Assignee: Lab Research CorporationInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
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Publication number: 20170076945Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
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Patent number: 9543148Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.Type: GrantFiled: September 1, 2015Date of Patent: January 10, 2017Assignee: Lam Research CorporationInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
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Publication number: 20160163558Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.Type: ApplicationFiled: July 20, 2015Publication date: June 9, 2016Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
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Patent number: 8730780Abstract: A light source and a waveguide are mounted on a recording head slider. Light rays are emitted from the light source into the waveguide. The waveguide may include two core layers for light ray transmission. The first core layer enhances light coupling efficiency from the light source to the second core layer. The second core layer transforms a profile of the light. The waveguide may include a tapered portion with a narrow opening near the light source and a wider opening near the tapered portion exit. The light rays passing through the waveguide may be directed toward a collimating mirror. The collimating mirror makes the light rays parallel or nearly parallel and re-directs the light rays to a focusing mirror. The focusing mirror focuses the collimated light rays to a spot on a magnetic media disc.Type: GrantFiled: February 22, 2013Date of Patent: May 20, 2014Assignee: Seagate TechnologyInventors: Chubing Peng, Edward Charles Gage, Kalman Pelhos
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Publication number: 20130230279Abstract: A light source and a waveguide are mounted on a recording head slider. Light rays are emitted from the light source into the waveguide. The waveguide may include two core layers for light ray transmission. The first core layer enhances light coupling efficiency from the light source to the second core layer. The second core layer transforms a profile of the light. The waveguide may include a tapered portion with a narrow opening near the light source and a wider opening near the tapered portion exit. The light rays passing through the waveguide may be directed toward a collimating mirror. The collimating mirror makes the light rays parallel or nearly parallel and re-directs the light rays to a focusing mirror. The focusing mirror focuses the collimated light rays to a spot on a magnetic media disc.Type: ApplicationFiled: February 22, 2013Publication date: September 5, 2013Applicant: SEAGATE TECHNOLOGY LLCInventors: Chubing Peng, Edward Charles Gage, Kalman Pelhos
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Patent number: 8385183Abstract: A light source and a waveguide are mounted on a recording head slider. Light rays are emitted from the light source into the waveguide. The waveguide may include two core layers for light ray transmission. The first core layer enhances light coupling efficiency from the light source to the second core layer. The second core layer transforms a profile of the light. The waveguide may include a tapered portion with a narrow opening near the light source and a wider opening near the tapered portion exit. The light rays passing through the waveguide may be directed toward a collimating mirror. The collimating mirror makes the light rays parallel or nearly parallel and re-directs the light rays to a focusing mirror. The focusing mirror focuses the collimated light rays to a spot on a magnetic media disc.Type: GrantFiled: November 5, 2009Date of Patent: February 26, 2013Assignee: Seagate Technology, LLCInventors: Chubing Peng, Edward Charles Gage, Kalman Pelhos
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Patent number: 8187480Abstract: Methods comprising providing a pre-patterned substrate having an array of thick walls, depositing a conforming layer on the pre-patterned substrate, etching the conforming layer from the top of the thick walls and the space between the walls, and etching the thick walls while leaving thin walls of conforming layer.Type: GrantFiled: November 13, 2008Date of Patent: May 29, 2012Assignee: Seagate Technology, LLCInventors: Kim Yang Lee, David S. Kuo, Dorothea Buechel, Kalman Pelhos
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Publication number: 20110103201Abstract: A light source and a waveguide are mounted on a recording head slider. Light rays are emitted from the light source into the waveguide. The waveguide may include two core layers for light ray transmission. The first core layer enhances light coupling efficiency from the light source to the second core layer. The second core layer transforms a profile of the light. The waveguide may include a tapered portion with a narrow opening near the light source and a wider opening near the tapered portion exit. The light rays passing through the waveguide may be directed toward a collimating mirror. The collimating mirror makes the light rays parallel or nearly parallel and re-directs the light rays to a focusing mirror. The focusing mirror focuses the collimated light rays to a spot on a magnetic media disc.Type: ApplicationFiled: November 5, 2009Publication date: May 5, 2011Applicant: Seagate Technology LLCInventors: Chubing Peng, Edward Charles Gage, Kalman Pelhos
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Patent number: 7869309Abstract: An apparatus comprises a waveguide, an optical transducer for coupling electromagnetic radiation from the waveguide to a point adjacent to an air bearing surface to heat a portion of a storage medium, and a first wire positioned adjacent to the air bearing surface, wherein current in the wire produces a magnetic field in the heated portion of the storage medium.Type: GrantFiled: August 11, 2005Date of Patent: January 11, 2011Assignee: Seagate Technology LLCInventors: Christophe Daniel Mihalcea, William Albert Challener, Werner Scholz, Kalman Pelhos, Dorothea Buechel, Julius Hohlfeld, Nils Jan Gokemeijer
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Patent number: 7824562Abstract: A method of fabricating a bit patterned storage medium includes obtaining a substrate having a magnetic layer and forming a mask over the magnetic layer. The magnetic layer is etched through the mask using a reactive ion etch. The etch rate of the mask is reduced by introducing a gas into the reactive ion etch.Type: GrantFiled: June 28, 2007Date of Patent: November 2, 2010Assignee: Seagate Technology LLCInventor: Kalman Pelhos
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Publication number: 20100119778Abstract: Methods comprising providing a pre-patterned substrate having an array of thick walls, depositing a conforming layer on the pre-patterned substrate, etching the conforming layer from the top of the thick walls and the space between the walls, and etching the thick walls while leaving thin walls of conforming layer.Type: ApplicationFiled: November 13, 2008Publication date: May 13, 2010Applicant: Seagate Technology LLCInventors: Kim Yang Lee, David S. Kuo, Dorothea Buechel, Kalman Pelhos
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Patent number: 7593278Abstract: A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell.Type: GrantFiled: August 21, 2007Date of Patent: September 22, 2009Assignee: Seagate Technology LLCInventors: Yufeng Hu, Michael Seigler, Kalman Pelhos
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Publication number: 20090052222Abstract: A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell.Type: ApplicationFiled: August 21, 2007Publication date: February 26, 2009Applicant: Seagate Technology LLCInventors: Yufeng Hu, Michael Seigler, Kalman Pelhos