Patents by Inventor Kamal K. Sikka
Kamal K. Sikka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210233892Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.Type: ApplicationFiled: January 25, 2020Publication date: July 29, 2021Inventors: Kamal K. Sikka, Paul S. Andry, Yang Liu, Pascale Gagnon, Christian Bergeron, Maryse Cournoyer
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Publication number: 20210233824Abstract: An integrated circuit (IC) package, and a method for fabricating an IC package is described. A set of semiconductor chips, a set of corner guard structures and a chip carrier are provided. The set of semiconductor chips and the set of corner guard structure placed and bonded to a first surface of the chip carrier. The set of semiconductor chips are in electrical contact with the chip carrier. Respective corner guard structures are placed proximate to the corners of respective semiconductor chips. The coefficient of thermal expansion (CTE) of the set of corner guard structures is selected to ameliorate chip-package interaction (CPI) related failures due to differences between a CTE of the set of semiconductor chips and a CTE of the chip carrier.Type: ApplicationFiled: January 23, 2020Publication date: July 29, 2021Inventors: Shidong Li, Kamal K. Sikka, Charles L. Arvin, Steven P. Ostrander
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Patent number: 11056418Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each microcooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: December 13, 2019Date of Patent: July 6, 2021Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 11049789Abstract: A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: December 13, 2019Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 11049844Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.Type: GrantFiled: July 1, 2019Date of Patent: June 29, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James Kelly, Kamal K. Sikka, Joshua M. Rubin
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Publication number: 20210183753Abstract: In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Katsuyuki Sakuma, Shidong Li, Kamal K. Sikka
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Patent number: 11035625Abstract: A heat sink includes a threaded rod. The threaded rod includes a first portion and a second portion. The first portion may engage with a first heat sink fin and a second portion may engage with a second heat sink fin. The first portion includes a first external thread of a first diameter. The second portion includes a second external thread also of the first diameter and of different pitch than the first external thread. For example, the pitch of a first knurl of the threaded rod may be smaller than the pitch of a second threaded knurl of the threaded rod. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.Type: GrantFiled: July 23, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Paul F. Bodenweber, Kamal K. Sikka
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Publication number: 20210159141Abstract: The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Kamal K. Sikka, Hiroyuki Mori
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Publication number: 20210134724Abstract: Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.Type: ApplicationFiled: November 1, 2019Publication date: May 6, 2021Inventors: Joshua M. Rubin, Kamal K. Sikka, Steven Lorenz Wright, Lawrence A. Clevenger
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Patent number: 10991635Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: GrantFiled: July 20, 2019Date of Patent: April 27, 2021Assignee: International Business Machines CorporationInventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Cournoyer
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Publication number: 20210118854Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
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Patent number: 10978314Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.Type: GrantFiled: October 3, 2019Date of Patent: April 13, 2021Assignee: International Business Machines CorporationInventors: Marcus E. Interrante, Kathryn R. Lange, Kamal K. Sikka, Tuhin Sinha, Hilton T. Toy, Jeffrey A. Zitz
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Publication number: 20210098334Abstract: Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Kamal K. Sikka, Piyas Bal Chowdhury, James J. Kelly, Jeffrey Allen Zitz, Sushumna Iruvanti, Shidong Li
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Patent number: 10948247Abstract: A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod may include a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.Type: GrantFiled: July 23, 2019Date of Patent: March 16, 2021Assignee: International Business Machines CorporationInventors: Paul F. Bodenweber, Kamal K. Sikka
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Patent number: 10937764Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.Type: GrantFiled: March 13, 2019Date of Patent: March 2, 2021Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
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Patent number: 10905029Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.Type: GrantFiled: October 29, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul F. Bodenweber, Kenneth C. Marston, Kamal K. Sikka, Hilton T. Toy, Randall J. Werner, Jeffrey A. Zitz
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Publication number: 20210022239Abstract: An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Kamal K. SIKKA, Chenzhou LIAN, Kathryn C. RIVERA, Paul F. BODENWEBER, Jon A. CASEY
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Publication number: 20210020529Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: ApplicationFiled: July 20, 2019Publication date: January 21, 2021Inventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Courmoyer
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Publication number: 20210005573Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James Kelly, Kamal K. Sikka, JOSHUA M. RUBIN
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Publication number: 20200402889Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Inventors: RAVI K. BONAM, Kamal K. Sikka, JOSHUA M. RUBIN, Iqbal Rashid Saraf, FEE LI LIE