Abstract: An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

Abstract: A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.

Abstract: A heat spreader is disclosed with regions where material is absent to reduce the mass/weight of the heat spreader without substantially reducing the temperature of the semiconductor chip and without substantially affecting the warpage and mechanical stress/strain in the electronic package.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.

Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each mircocooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover.

Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

Abstract: A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.

Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.

Abstract: An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod includes a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover.