Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Abstract: A solid-state imaging device that includes a first substrate, one or multiple second substrates, a first wiring layer, a second wiring layer, and a first alignment part. The first substrate includes a first semiconductor substrate with multiple photoelectric conversion sections, and a multilayer wiring layer. The one or multiple second substrates are attached to the first substrate with the multilayer wiring layer interposed therebetween. The first wiring layer is in the multilayer wiring layer and includes multiple first thin metal wires formed at substantially the same first pitches. The second wiring layer is stacked above the first wiring layer in the multilayer wiring layer and includes multiple second thin metal wires formed between the multiple first thin metal wires at substantially the same second pitches in a plan view. The first alignment part is formed above the second wiring layer in the multilayer wiring layer.

Abstract: The present technology relates to an imaging element and a semiconductor chip that can implement a low height of the imaging element. A first chip including a photo diode; and a second chip including a circuit processing a signal transmitted from the photo diode are stacked, and a charging film is disposed on a second face of the second chip that is on a side opposite to a first face on which the first chip is stacked. The charging film is disposed in a part or the entirety of the second face. For example, the present technology can be applied to an imaging element, in which a plurality of chips are configured to be stacked, that can implement a low height and a small size.

Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

Abstract: A light emitting element and display device are disclosed. In one example, a light emitting element includes a first electrode formed on a base body. A first insulation layer is formed on the base body and the first electrode and has an aperture portion in which a part of the first electrode is exposed. A second insulation layer is formed on the first insulation layer and has a protruding end portion protruding from the aperture portion. A third insulation layer is formed on the second insulation layer and has an end portion recessed from the protruding end portion. A charge injection/transport layer is formed over the second insulation layer and the third insulation layer. An organic layer includes a light emitting layer, and a second electrode formed on the organic layer. At least a part of the charge injection/transport layer is discontinuous at the protruding end portion.

Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device serving as an embodiment of the present disclosure includes: a storage element; a first contact that is electrically coupled to this storage element; a second contact that is positioned on an opposite side to the first contact in a first direction; a protective film that surrounds the storage element in a first plane orthogonal to the first direction; and a first hydrogen block layer that surrounds the protective film in the first plane. The second contact is electrically coupled to the storage element.

Abstract: There is provided a semiconductor device having a configuration suitable for higher integration. The semiconductor device includes: a first substrate having a first front surface; and a second substrate having a second front surface joined to the first front surface. The first substrate includes a first wiring layer including a first wiring line, and a first semiconductor layer that are stacked in order from a position close to the second substrate, and the second substrate includes a storage element layer including a storage element, and a second semiconductor layer that are stacked in order from a position close to the first substrate.

Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

Abstract: A light emitting element and display device are disclosed. In one example, a light emitting element includes a first electrode formed on a base body. A first insulation layer is formed on the base body and the first electrode and has an aperture portion in which a part of the first electrode is exposed. A second insulation layer is formed on the first insulation layer and has a protruding end portion protruding from the aperture portion. A third insulation layer is formed on the second insulation layer and has an end portion recessed from the protruding end portion. A charge injection/transport layer is formed over the second insulation layer and the third insulation layer. An organic layer includes a light emitting layer, and a second electrode formed on the organic layer. At least a part of the charge injection/transport layer is discontinuous at the protruding end portion.

Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

Abstract: A light emitting element and display device are disclosed. In one example, a light emitting element includes a first electrode formed on a base body. A first insulation layer is formed on the base body and the first electrode and has an aperture portion in which a part of the first electrode is exposed. A second insulation layer is formed on the first insulation layer and has a protruding end portion protruding from the aperture portion. A third insulation layer is formed on the second insulation layer and has an end portion recessed from the protruding end portion. A charge injection/transport layer is formed over the second insulation layer and the third insulation layer. An organic layer includes a light emitting layer, and a second electrode formed on the organic layer. At least a part of the charge injection/transport layer is discontinuous at the protruding end portion.

Abstract: Provided is an electric charge detection sensor that has a plurality of electrodes arranged in an array and detects electric charge generated in solution on each electrode, in which a sensing sensitivity is improved. The electric charge detection sensor includes a plurality of detection electrodes that is arranged in an array and detects electric charge. The plurality of detection electrodes is insulated from each other by an insulating portion. A group of conductive particles is deposited on surfaces of the plurality of detection electrodes. This allows for formation of a three-dimensional electrode on the surface of each detection electrode, an increase in surface area of each detection electrode, and a reduction in resistance.

Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

Abstract: A light emitting element and display device are disclosed. In one example, a light emitting element includes a first electrode formed on a base body. A first insulation layer is formed on the base body and the first electrode and has an aperture portion in which a part of the first electrode is exposed. A second insulation layer is formed on the first insulation layer and has a protruding end portion protruding from the aperture portion. A third insulation layer is formed on the second insulation layer and has an end portion recessed from the protruding end portion. A charge injection/transport layer is formed over the second insulation layer and the third insulation layer. An organic layer includes a light emitting layer, and a second electrode formed on the organic layer. At least a part of the charge injection/transport layer is discontinuous at the protruding end portion.

Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.