Abstract: A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.

Abstract: An internal voltage generating circuit of a semiconductor device includes a normal reference voltage generating unit configured to generate a normal reference voltage having a constant voltage level without regard to PVT variations, a test reference voltage generating unit configured to generate a test reference voltage by dividing a voltage level between an external power supply voltage and the normal reference voltage at a set ratio, an operation reference voltage generating unit configured to generate an operation reference voltage by selecting one of the normal reference voltage and the test reference voltage in response to a test signal, and an internal voltage generating unit configured to generate an internal voltage whose voltage level is determined based on the level of the operation reference voltage.

Abstract: Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.

Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.

Abstract: A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.

Abstract: A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period.

Abstract: A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.

Abstract: An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other.

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract: A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.

Abstract: A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption.

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.

Abstract: A negative voltage supply device includes a negative voltage detector and a negative voltage pumping unit. The negative voltage pumping unit pumps a negative voltage in response to a detection signal. The negative voltage detector detects a level of a negative voltage by using a first element and a second element, which are different in the degree of change in their respective resistance values depending on the temperature, and outputs the detection signal. The detection signal informs the negative voltage pumping unit that pumping of the negative voltage is no longer needed.

Abstract: Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.

Abstract: There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract: A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.