Patents by Inventor Kang Seol Lee

Kang Seol Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7969795
    Abstract: A negative voltage generator of a semiconductor memory device includes: a flag signal generation unit for receiving a temperature information code from an On Die Thermal Sensor (ODTS) to output a plurality of flag signals containing temperature information of the semiconductor memory device; and a negative voltage detection unit for detecting a negative voltage to output a detection signal for determining whether to pump a negative voltage, wherein a detection level of the negative voltage is changed according to the flag signals.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 28, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang-Seol Lee
  • Patent number: 7969800
    Abstract: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: June 28, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Sik Yun, Kang Seol Lee
  • Patent number: 7948823
    Abstract: A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: May 24, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Sik Yun, Kang-Seol Lee
  • Patent number: 7936614
    Abstract: A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: May 3, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Ho Kim, Kang-Seol Lee
  • Publication number: 20110068821
    Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.
    Type: Application
    Filed: December 2, 2010
    Publication date: March 24, 2011
    Inventors: Tae-Sik YUN, Kang-Seol Lee
  • Patent number: 7898287
    Abstract: An input buffer includes a delay compensation unit for combining (a) a first signal obtained by buffering an input signal using another signal, which is out of phase with the input signal, with (b) a second signal obtained by buffering the input signal using a reference voltage signal, to output a third signal.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: March 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Ho Kim, Kang Seol Lee
  • Patent number: 7889574
    Abstract: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: February 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Jin Byeon, Kang-Seol Lee
  • Patent number: 7885135
    Abstract: A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kang-Seol Lee, Seok-Cheol Yoon
  • Patent number: 7868647
    Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Sik Yun, Kang-Seol Lee
  • Publication number: 20100232239
    Abstract: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.
    Type: Application
    Filed: June 29, 2009
    Publication date: September 16, 2010
    Inventors: Tae Sik Yun, Kang Seol Lee
  • Patent number: 7782647
    Abstract: A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Souk Lee, Kang-Seol Lee
  • Publication number: 20100188139
    Abstract: A negative voltage supply device includes a negative voltage detector and a negative voltage pumping unit. The negative voltage pumping unit pumps a negative voltage in response to a detection signal. The negative voltage detector detects a level of a negative voltage by using a first element and a second element, which are different in the degree of change in their respective resistance values depending on the temperature, and outputs the detection signal. The detection signal informs the negative voltage pumping unit that pumping of the negative voltage is no longer needed.
    Type: Application
    Filed: March 18, 2010
    Publication date: July 29, 2010
    Inventor: Kang-Seol LEE
  • Publication number: 20100118580
    Abstract: A semiconductor memory device includes first positive and negative data lines driven with voltage levels contrary to each other in response to first data and second positive and negative data lines driven with voltage levels contrary to each other in response to second data, wherein one of the second positive and negative data lines is disposed between the first positive and negative data lines.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 13, 2010
    Inventors: Kang-Seol Lee, Young-Jun Ku
  • Publication number: 20100109701
    Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.
    Type: Application
    Filed: December 24, 2008
    Publication date: May 6, 2010
    Inventors: Tae-Sik YUN, Kang-Seol Lee
  • Publication number: 20100097873
    Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 22, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kang Seol Lee, Eun Souk Lee
  • Publication number: 20100073078
    Abstract: There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.
    Type: Application
    Filed: December 3, 2009
    Publication date: March 25, 2010
    Inventors: Kang-Seol LEE, Jae-Hyuk Im
  • Publication number: 20100061159
    Abstract: A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.
    Type: Application
    Filed: December 16, 2008
    Publication date: March 11, 2010
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Ki-Ho KIM, Kang-Seol Lee
  • Publication number: 20100061177
    Abstract: A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.
    Type: Application
    Filed: December 29, 2008
    Publication date: March 11, 2010
    Inventors: Tae-Sik Yun, Kang-Seol Lee
  • Patent number: 7672174
    Abstract: A semiconductor memory device includes an equalizing signal generation circuit comprising a clamping circuit that clamps a voltage level less than the voltage level of a high voltage level by being controlled by the high voltage, and an equalizing signal driver receiving an output signal of the equalizing signal generation circuit as a driving signal.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Kang-Seol Lee
  • Patent number: 7663931
    Abstract: A semiconductor memory device includes a low voltage supplier for supplying a low voltage lower than a ground voltage; a voltage selector for selecting one of the low voltage and the ground voltage; and a word line driving circuit for driving a word line in response to an output of the voltage selector. The voltage selector operates when a self refresh signal is inputted, and supplies the low voltage as a voltage of logic low level used in the word line driving circuit in a self refresh mode and supplies the ground voltage as a voltage of logic low level used in the word line driving circuit in modes other than the self refresh mode.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: February 16, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kang-Seol Lee, Seok-Cheol Yoon