Abstract: The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

Abstract: Apparatus and methods for protecting in-flight data during a fundamental reset of a SSD by a connected host are presented. In embodiments, a controller for the SSD includes an input interface configured to receive commands from the host over a link, and processing circuitry coupled to the input interface. The processing circuitry is configured to, in response to receiving a reset command from the host, reset the link and an address space of the SSD, complete a flush of in-flight data from temporary buffers to non-volatile storage of the SSD, and, during an initialization sequence performed by the host, perform an internal reset. In embodiments, in response to the SSD performing the internal reset, the host's state of the SSD is reset, and the host is caused to re-initialize the link and configure the address space of the SSD.

Abstract: A method for augmenting a computing device is disclosed comprising providing a data storage arrangement, the data storage arrangement having a memory having a partition of a first section and a sub dividable second section, monitoring the computing device to determine when the first section of memory requires augmentation, subdividing the second section of the memory into a transferable section memory and a remainder section memory and augmenting the first section of the memory with the transferable section.

Abstract: In one embodiment, there is a method for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address. The method comprises performing a folding operation data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory, receiving a read request to read data associated with a first logical block address, identifying that the first virtual address is associated with the first logical block address, determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria. In response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address.

Abstract: A method and apparatus for optimizing read operations during a control sync operation on a data storage device are disclosed. The data storage device contains a management table used for mapping memory addresses to a non-volatile memory. A control sync operation makes a copy of the management table to the non-volatile memory. The control sync operation is non-blocking—the sync operation allows read and write operations in parallel with making a copy of or updating the management table. During the control sync operation, the read operations are optimized through a CUQ and an overlap range table. The CUQ may act as a temporary management table while also containing updates to be consolidated to the management table. The overlap range table is used to allow skipping searches within the CUQ by identifying then mapping entries that reside within CUQ.

Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method includes generating a prior read command data structure and receiving a current read command. The method may include retrieving from the prior read command data structure a predicted next read command based on the received current read command, and pre-fetching data associated with the predicted next read command. The method may further include that after pre-fetching the data associate with the predicted next read command and prior to receiving a next read command, retrieving from the prior read command data structure a second predicted next read command based on the predicted next read command, and pre-fetching data associated with the second predicted next read command.

Abstract: An apparatus includes a plurality of non-volatile memory cells and control circuitry connected to the plurality of non-volatile memory cells. The control circuitry is configured to receive write commands from a host and identify write commands associated with temporary data. In a recovery operation, control data associated with the temporary data is omitted from rebuilt control data.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.

Abstract: Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device.

Abstract: A method and apparatus for selecting power states in storage devices for computers including providing monitoring storage device parameters and comparing those parameters to endurance thresholds to increase reliability of the storage device.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: A method and apparatus for selecting power states in storage devices for computers including providing monitoring storage device parameters and comparing those parameters to endurance thresholds to increase reliability of the storage device.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.

Abstract: A method for augmenting a computing device is disclosed comprising providing a data storage arrangement, the data storage arrangement having a memory having a partition of a first section and a sub dividable second section, monitoring the computing device to determine when the first section of memory requires augmentation, subdividing the second section of the memory into a transferable section memory and a remainder section memory and augmenting the first section of the memory with the transferable section.

Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.

Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.