Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.

Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.

Abstract: A method and apparatus for optimizing read operations during a control sync operation on a data storage device are disclosed. The data storage device contains a management table used for mapping memory addresses to a non-volatile memory. A control sync operation makes a copy of the management table to the non-volatile memory. The control sync operation is non-blocking—the sync operation allows read and write operations in parallel with making a copy of or updating the management table. During the control sync operation, the read operations are optimized through a CUQ and an overlap range table. The CUQ may act as a temporary management table while also containing updates to be consolidated to the management table. The overlap range table is used to allow skipping searches within the CUQ by identifying then mapping entries that reside within CUQ.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory. The non-volatile memory is configured to store the second data and the updated control information in a non-blocking manner.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory.

Abstract: A storage device may be configured to copy valid data units from a source memory area to a destination memory area according to a source-to-destination mapping. The source-to-destination mapping may be generated based on a ranking scheme that considers the number of valid data units being stored in each of a plurality of source pages storing the data.

Abstract: In a non-volatile memory system, the controller maintains in its volatile memory two free block lists for the assignment of memory circuit blocks when writing user and system data. Copies of the free block lists are maintained in the non-volatile memory. While allocating blocks from a first of the free block lists, the controller can update a second of the free block lists as part of a control sync operation preparing control data stored in non-volatile memory. This allows the memory system to operate in a non-blocking manner during the control sync. Once the second free block lists is prepared and the control sync completed, the second block can subsequently be used for block allocations and a control sync operation can be done to update the first block.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory.

Abstract: A storage device may be configured to copy valid data units from a source memory area to a destination memory area according to a source-to-destination mapping. The source-to-destination mapping may be generated based on a ranking scheme that considers the number of valid data units being stored in each of a plurality of source pages storing the data.

Abstract: Systems, apparatuses, and methods are provided for write abort detection. A memory system may write data to one or more cells in a memory. An abrupt shutdown may interrupt the write, resulting in an uncertainty as to the state of the memory cells. In order to determine the state of the memory cells, after power-up, a first section of memory that includes the memory cells is analyzed, such as counting values of logic “0”s stored in the memory cells of the first section of memory. However, the values in the first section of memory may be subject to error, hindering the accuracy of write abort detection. In order to reduce or cancel the effect of the errors, a second section of memory (which may suffer from similar errors as the first section) is analyzed, such as by counting values of logic “0”s stored in the memory cells of the second section of memory.

Abstract: The present disclosure provides one or network devices having a shared resource that can be remotely accessed by multiple users, also referred to as tenants. The shared resource can be located within one network device or can be spread throughout multiple network devices. One or more resources from among the shared resource can be allocated to one or more corresponding tenants from among the multiple tenants. The one or more corresponding tenants can access their respective resources using one or more commands. The one or network devices can implement an authorization procedure to ensure that the one or more tenants can only access their respective resources. The authorization procedure represents an access control mechanism to grant access to the one or more tenants to only their respective resources.