Abstract: Diffusion barriers are used in integrated circuits. The present method of depositing diffusion barriers eliminates the formation of high resistivity phases, providing high electrical conductivity and diffusion suppression between the interconnect conductors, for example copper, and the semiconductor device. In a preferred embodiment, the diffusion barrier is formed by depositing a film of binary transition metal nitride then treating the film in a gas containing silicon in order to form a layer of silicon rich material on the surface of the binary transition metal nitride film.

Abstract: An apparatus and method for controlling and optimizing a non-planar target shape of a sputtering magnetron system are employed to minimize the redeposition of the sputtered material and optimize target erosion. The methodology is based on the integration of sputtered material from each point of the target according to its solid angle view of the rest of the target. The prospective target's geometry is optimized by analytically comparing and evaluating the methodology's results of one target geometry against that of another geometry, or by simply altering the first geometry and recalculating and comparing the results of the first geometry against the altered geometry. The target geometries may be of many different shapes including trapezoidal, cylindrical, parabolic, and elliptical, depending upon the optimum process parameters desired.

Abstract: A magnetron source comprises a hollow cathode with a non-planar target. By using a magnet between the cathode and a substrate, plasma can be controlled to achieve high ionization levels, good step coverage, and good process uniformity. Step coverage uniformity is also improved by controlling the magnetic fields, and thus the flow of ions and electrons, near the plane of the substrate.

Abstract: A multi-level shelf degas station relying on at least two heaters integrated within wafer holding shelves or slots, where the semiconductor wafers do not have direct contact with the heater shelves. The heaters provide conduction heating. In order to degas a wafer, the heater and wafer holder assembly is positioned in a sequential manner through each wafer slot to the next available slot. If a degassed wafer exists in the slot, a transfer chamber arm removes it. A loader arm then places a wafer in the available, empty slot and the stage is moved upwards to receive the wafer from the loader arm. The transfer chamber arm removes an individual wafer from the heater and wafer holder assembly allowing the removed wafer to be individually processed while the other wafers remain in the heater and wafer holder assembly. In some instances, a loader arm may also remove wafers.

Abstract: A novel hollow cathode magnetron source is disclosed. The source comprises a hollow cathode with a non-planar target. By using a magnet between the cathode and a substrate, plasma can be controlled to achieve high ionization levels, good step coverage, and good process uniformity.

Abstract: A hollow cathode magnetron (HCM) sputter source includes a main magnet positioned near the sidewall of the hollow cathode target and a pair of rotating magnet arrays that are positioned near the closed end of the hollow cathode target. One of the arrays produces a magnetic field that is aligned with (aids) the magnetic field produced by the main magnet; the other arrays produce a magnetic field that is aligned against (bucks) the magnetic field produced by the main magnet. Field lines produced by the magnet arrays contain an extension of the plasma that is controlled by the main magnet. Charged particles circulate between the two portions of the plasma. The extended plasma is thus formed over a very high percentage of the surface of the target, thereby creating an erosion profile that is highly uniform and encompasses essentially the entire face of the target. This maximizes the utilization of the target and minimizes the frequency at which the spent target must be replaced.

Abstract: A novel hollow cathode magnetron source is disclosed. The source comprises a hollow cathode with a non-planar target. By using a magnet between the cathode and a substrate, plasma can be controlled to achieve high ionization levels, good step coverage, and good process uniformity.

Abstract: Disclosed is a system, including both method and apparatus, for enhancing the plasma etching of a semiconductor wafer. The system enhances etchant uniformity while greatly reducing plasma contamination. Etching is performed in a housing for processing a semiconductor wafer having a wafer perimeter defined by an outer wafer edge, a top surface and a bottom surface. The plasma etch technique includes a plasma positioned substantially coplanar with and proximate,to the semiconductor wafer. The plasma has a perimeter defined by an outer plasma edge and extending beyond substantially all of the wafer perimeter. Provided is a means for introducing an inert gas between the wafer perimeter and the plasma perimeter so the inert gas may or may not hit the wafer's bottom surface. Plasma and wafer can each have a circular shape where the plasma and the wafer are proximate to each other.

Abstract: Multilayer diffusion barriers are used in integrated circuits. These diffusion barriers provide high electrical conductivity to carry current efficiently with fast response time, and additionally suppress diffusion between interconnect conductors, e.g. Cu, and the semiconductor device. Moreover, the present multilayer diffusion barriers adhere well to the underlying materials as well as to Cu.In a preferred embodiment, the diffusion barriers comprise bilayers, each containing a first sublayer formed of a refractory metal, or a refractory metal nitride; and a second sublayer formed of a refractory metal nitride, a refractory metal silicon nitride, a refractory metal silicon boride, or a refractory metal oxonitride.Multilayer diffusion barriers are deposited easily by CVD in a multistation module. The present structures can be applied to sub-0.25 .mu.m logic, memory and application specific circuits with Cu as the primary conductor.

Abstract: A reflective method for monitoring the etch rate or growth rate of a material, such as a semiconductor material, that may be initially at least partly covered by another layer of a different material. An aperture in the overlying material is formed to expose a portion of the surface of the layer to be etched or grown, and a monochromatic light beam is directed at the exposed surface to form a signal which can be used to monitor the processing of the material.

Abstract: Disclosed is a system, including both method and apparatus, for enhancing the plasma etching of a semiconductor wafer. The system enhances etchant uniformity while greatly reducing plasma contamination. Etching is performed in a housing for processing a semiconductor wafer having a wafer perimeter defined by an outer wafer edge, a top surface and a bottom surface. The plasma etch technique includes a plasma positioned substantially coplanar with and proximate to the semiconductor wafer. The plasma has a perimeter defined by an outer plasma edge and extending beyond substantially all of the wafer perimeter. Provided is a means for introducing an inert gas between the wafer perimeter and the plasma perimeter so the inert gas may or may not hit the wafer's bottom surface. Plasma and wafer can each have a circular shape where the plasma and the wafer are proximate to each other.

Abstract: Magnetic confinement of electrons in a plasma reactor is effected using electro-magnetic coils and other magnets which generate respective magnetic fields which are mutually opposed and substantially orthogonal on their common axis to the major plane of a wafer being processed, instead of being aligned and parallel to the major plane as in prior magnetically enhanced plasma reactors. The respective magnetic fields combine to yield a net magnetic field which is nearly parallel to the wafer away from the magnetic axis so that electrons are confined in the usual manner. In addition, a magnetic mirror provides confinement near the magnetic axis. The E.times.B cross product defines a circumferential drift velocity urging electrons about a closed path about the magnetic axis.

Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.

Abstract: A process is described for plasma-assisted etching of an aluminum layer to form aluminum lines while fabricating an integrated circuit structure on a semiconductor wafer using one or more bromine-containing etch gases, and optionally SF.sub.6 in combination with the bromine-containing gas or gases, which will not result in the formation of corrosive residues such as normally occurs when chlorine-based etchants are used.

Abstract: A process is disclosed for accurately forming an etch mask over the uneven surface of a semiconductor wafer using a multilayer photoresist. The process comprises forming a first or lower photoresist layer on the surface of a semiconductor wafer, forming one or more intermediate layers over the first photoresist layer, forming a second or upper photoresist layer over the one or more intermediate layers on the wafer, photolithographically forming a pattern in the second photoresist layer, reproducing the pattern in the intermediate layer below the second photoresist layer, removing the remainder of the upper photoresist layer, and then reproducing the pattern in the first photoresist layer using the pattern formed in the intermediate layer as a mask. In one embodiment a single intermediate layer is used in which the mask pattern is partially etched prior to removal of the upper photoresist.