Abstract: A void fraction sensor according to the present disclosure includes an insulating inner pipe having a through hole through which a low-temperature liquid flows, at least a pair of electrodes mounted on an outer peripheral surface of the insulating inner pipe, and a heat insulating layer covering an outer peripheral side of the insulating inner pipe. A flowmeter according to the present disclosure measures a flow rate of a cryogenic liquid flowing through the through hole of the insulating inner pipe, and includes the void fraction sensor described above, and a flow velocity meter that measures a flow velocity of the cryogenic liquid flowing through the through hole.

Abstract: A void fraction sensor according to the present disclosure includes an insulating pipe having a through hole through which a cryogenic liquid flows, and a pair of planar electrodes mounted on an outer wall surface of the insulating pipe. The insulating pipe has electrode mounting portions at which a distance D1 between inner wall surfaces in a direction perpendicular to electrode surfaces of the pair of planar electrodes is shorter than a distance D2 between inner wall surfaces in a direction parallel to the electrode surfaces of the pair of planar electrodes.

Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

Abstract: Based on operation trajectory data an operation analysis device identifies all open points indicating positions at which the crusher is opened during the operation period and all close points indicating positions at which a crusher is closed during an operation period, calculates, as a shortest distance, a distance between each open point of the all open points and a close point nearest to the each open point, and identifies, as a sorting destination open point, an open point at which the shortest distance exceeds a first threshold value, identifies data until the crusher grasping the dismantling part moves to the sorting destination and returns to the dismantling target again from among the operation trajectory data as movement data of the crusher having moved in the dismantling operation, and identifies data in which the movement data has been removed from the operation trajectory data as grasping operation data.

Abstract: A void fraction sensor for measuring a void fraction of a cryogenic liquid includes a pipe having a flow channel in which a cryogenic liquid flows, a first electrode and a second electrode disposed outside the flow channel, and at least one intermediate electrode disposed in the flow channel and between the first electrode and the second electrode, the at least one intermediate electrode measuring capacitance with the first electrode and/or the second electrode.

Abstract: A void fraction sensor for measuring a void fraction of a cryogenic liquid includes a pipe having a conduit in which the cryogenic liquid flows, and an electrode provided on the outer peripheral surface of the pipe to measure capacitance of the cryogenic liquid flowing in the conduit. The pipe is composed of an even number of dividable ceramic members, and among the even number of ceramic members, at least two ceramic members facing each other are each provided with the electrode.

Abstract: In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A crack generated on a main surface of a substrate is detected, and the main surface of the substrate is scanned with the laser light in order that a time integral of a light amount of laser light for annealing with which a unit area in a crack region including the detected crack is irradiated is smaller than a time integral of a light amount of the laser light with which a unit area in a region different from the crack region is irradiated, to perform laser annealing treatment on the substrate.

Abstract: To provide a robot control system and a robot control method capable of placing a component grasped by a robot hand at an accurate location on another member. A robot control system is provided with: a robot hand configured to grasp a clip; a camera configured to capture an image of the clip grasped by the robot hand, a calculation unit configured to calculate a position of the clip or an inclination of a component based on an imaging result of the clip captured by the camera, and a robot control unit configured to control the robot hand to adjust, based on the position of the clip or the inclination of the component calculated by the calculation unit, a position or an inclination of the robot hand and move the clip to a stringer.

Abstract: In an RFC diode, a semiconductor substrate includes an n? drift layer, an n buffer layer, and a diffusion layer provided between and in contact with the n buffer layer and a second metal layer. The diffusion layer includes an n+ cathode layer provided in contact with the n buffer layer and the second metal layer in a diode region. The n+ cathode layer includes a first n+ cathode layer in contact with the second metal layer and a second n+ cathode layer provided between the first n+ cathode layer and the n buffer layer in contact with the n buffer layer. Crystal defect density of the first n+ cathode layer is higher than crystal defect density of another diffusion layer.

Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.

Abstract: Hysteresis of gate leakage is reduced in a semiconductor device with a structure including embedded electrodes below gate trench electrodes. A semiconductor device includes an active trench gate formed in a trench coming in contact with an emitter layer, a base layer, and a carrier storage layer to reach a drift layer. The active trench gate includes: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode, and an embedded electrode below the gate trench electrode, the gate trench electrode and the embedded electrode being formed on the gate trench insulating film in the trench and being insulated from each other. The embedded electrode is lower in phosphorus concentration than the gate trench electrode.

Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.

Abstract: A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.

Abstract: A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm?3.

Abstract: A plain bearing includes: a bearing body; a radial bearing portion arranged on an inner peripheral surface of the bearing body; a thrust bearing portion arranged on an axial end surface of the bearing body; a damper portion arranged on an outer peripheral surface of the bearing body; a dam portion arranged on the outer peripheral surface of the bearing body; and an oil hole having an inlet that opens to at least one of the outer peripheral surface of the bearing body and the dam portion, and an outlet that opens to the inner peripheral surface of the bearing body. The inlet, at least a part of the dam portion, and the damper portion are arranged in this order from an axially inner side toward an axially outer side. An outlet of an upstream side oil passage is connected to the inlet on a radially outer side.

Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl