Patents by Inventor Katsutaka Kimura
Katsutaka Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120218819Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: ApplicationFiled: November 29, 2011Publication date: August 30, 2012Inventors: Masataka KATO, Tetsuo ADACHI, Toshihiro TANAKA, Toshio SASAKI, Hitoshi KUME, Katsutaka KIMURA
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Patent number: 8072809Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: GrantFiled: June 1, 2010Date of Patent: December 6, 2011Assignee: Solid State Storage Solutions, Inc.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Publication number: 20110051515Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: ApplicationFiled: June 1, 2010Publication date: March 3, 2011Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Publication number: 20100277996Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.Type: ApplicationFiled: February 8, 2008Publication date: November 4, 2010Inventors: Riichiro TAKEMURA, Kiyoo ITOH, Tomonori SEKIGUCHI, Takeshi SAKATA, Katsutaka KIMURA
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Patent number: 7821804Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.Type: GrantFiled: September 6, 2007Date of Patent: October 26, 2010Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Patent number: 7746697Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: GrantFiled: March 11, 2008Date of Patent: June 29, 2010Assignee: Solid State Storage Solutions, Inc.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 7582921Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.Type: GrantFiled: August 16, 2006Date of Patent: September 1, 2009Assignee: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Toshihiko Tanaka, Toshiaki Yamanaka, Takeshi Sakata, Katsutaka Kimura
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Publication number: 20090016102Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.Type: ApplicationFiled: May 9, 2008Publication date: January 15, 2009Inventors: Yusuke Jyouno, Takayuki Kawahara, Katsutaka Kimura
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Publication number: 20080219082Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: ApplicationFiled: March 11, 2008Publication date: September 11, 2008Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 7394697Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.Type: GrantFiled: November 13, 2006Date of Patent: July 1, 2008Assignee: Renesas Technology Corp.Inventors: Yusuke Jyouno, Takayuki Kawahara, Katsutaka Kimura
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Patent number: 7366016Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: GrantFiled: January 25, 2007Date of Patent: April 29, 2008Assignee: Solid State Storage Solutions, LLCInventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 7366015Abstract: A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.Type: GrantFiled: January 31, 2007Date of Patent: April 29, 2008Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Takashi Kobayashi, Hideaki Kurata, Naoki Kobayashi, Hitoshi Kume, Katsutaka Kimura, Shunichi Saeki
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Patent number: 7345938Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.Type: GrantFiled: May 9, 2007Date of Patent: March 18, 2008Assignee: Renesas Technology Corp.Inventors: Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Takeshi Sakata, Katsutaka Kimura
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Publication number: 20080002448Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.Type: ApplicationFiled: September 6, 2007Publication date: January 3, 2008Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Publication number: 20070297257Abstract: A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.Type: ApplicationFiled: August 17, 2007Publication date: December 27, 2007Inventors: Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Tsugio Takahashi, Yoshitaka Nakamura
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Patent number: 7289346Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.Type: GrantFiled: February 9, 2006Date of Patent: October 30, 2007Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Patent number: 7274613Abstract: A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.Type: GrantFiled: August 8, 2005Date of Patent: September 25, 2007Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Tsugio Takahashi, Yoshitaka Nakamura
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Publication number: 20070211547Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.Type: ApplicationFiled: May 9, 2007Publication date: September 13, 2007Inventors: Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Takeshi Sakata, Katsutaka Kimura
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Publication number: 20070195596Abstract: A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.Type: ApplicationFiled: January 31, 2007Publication date: August 23, 2007Inventors: Takashi Kobayashi, Hideaki Kurata, Naoki Kobayashi, Hitoshi Kume, Katsutaka Kimura, Shunichi Saeki
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Patent number: 7245532Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.Type: GrantFiled: January 17, 2006Date of Patent: July 17, 2007Assignee: Renesas Technology CorporationInventors: Yusuke Jyouno, Takayuki Kawahara, Katsutaka Kimura