Abstract: A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

Abstract: A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract: In a hetero bipolar transistor according to the present invention, a SiGe spacer layer (40), a SiGe graded layer (41) having a portion functioning as a base layer and composed of a plurality of sublayers having different Ge composition ratios, and a Si cap layer (42) are formed on a collector layer (12) formed in a portion of a Si substrate (10). In the SiGe graded layer (41), when the thickness of each sublayer is larger, the number of sublayers is smaller, and difference in Ge composition ratio between adjacent sublayers is larger, measurement of the thickness of each sublayer becomes easier. However, in order to avoid degradation of a cut-off frequency characteristic of a device, the film thickness of each sublayer needs to be approximately 20 nm or less, and the number of sublayers is preferably 2 or more.

Abstract: A stochastic processor and a stochastic computer comprises a fluctuation generator configured to generate and output analog quantity having fluctuation comprised of chaos of tent mapping, a mixer configured to output a fluctuation superposed signal with the analog quantity output from the fluctuation generator superposed on an input signal represented by analog quantity and a thresholding unit configured to perform thresholding on the fluctuation superposed signal output from the mixer to generate and output a pulse.

Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1<1 and O<yl<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1x-2-y2Gex2Cy2 layer (0<x2≦1 and 0≦y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract: An initial estimated value of a process condition is set, and a structure of an element of a semiconductor device is estimated by a process simulator, after which an estimated value of a physical amount measurement value is calculated. Then, an actual measurement value of a physical amount of the element of the semiconductor device, which is obtained by an optical evaluation method, and a theoretical calculated value thereof are compared with each other, so as to obtain a probable structure of the measured semiconductor device element by using, for example, a simulated annealing, or the like. A process condition in a process for other semiconductor device elements can be corrected by using the results.

Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A B-doped Si1−x−yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1−x−yGexCy layer 102 is annealed to form a B-doped Si1−x−yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.

Abstract: After the surface of a Si substrate (1) has been pretreated, an SiGeC layer (2) is formed on the Si substrate (1) using an ultrahigh vacuum chemical vapor deposition (UHV-CVD) apparatus. During this process step, the growth temperature of the SiGeC layer (2) is set at 490° C. or less and Si2H6, GeH4 and SiH3CH3 are used as Si, Ge and C sources, respectively, whereby the SiGeC layer (2) with good crystallinity can be formed.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Abstract: A B-doped Si1-x-yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1-x-yGexCy layer 102 is annealed to form a B-doped Si1-x-yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.