Abstract: A B-doped Si1−x−yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1−x−yGexCy layer 102 is annealed to form a B-doped Si1−x−yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.

Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

Abstract: Source gases and atomic hydrogen are alternately supplied onto a substrate on which a crystal is to be grown. By exposing a surface of the substrate to the atomic hydrogen, the ratio of Ge atoms attached to H atoms to all Ge atoms present on the outermost surface where growth is proceeding is increased compared with that prior to the exposure to the atomic hydrogen. If H atoms are attached to Ge atoms on the outermost surface, the phenomenon occurs in which the Ge atoms are interchanged with Si atoms present in the underlying layer. As a result, a higher proportion of Ge atoms are interchanged with Si atoms than in a conventional manufacturing method which does not involve the exposure to the atomic hydrogen. This reduces the ratio of Ge atoms to all atoms on the outermost surface where growth is proceeding and renders C atoms having low affinity with Ge atoms more likely to occupy lattice positions in the crystal.

Abstract: After the surface of a Si substrate 1 has been pretreated, an SiGeC layer 2 is formed on the Si substrate 1 using an ultrahigh vacuum chemical vapor deposition (UHV-CVD) apparatus. During this process step, the growth temperature of the SiGeC layer 2 is set at 490° C. or less and Si2H6, GeH4 and SiH3CH3 are used as Si, Ge and C sources, respectively, whereby the SiGeC layer 2 with good crystallinity can be formed.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: An initial estimated value of a process condition is set, and a structure of an element of a semiconductor device is estimated by a process simulator, after which an estimated value of a physical amount measurement value is calculated. Then, an actual measurement value of a physical amount of the element of the semiconductor device, which is obtained by an optical evaluation method, and a theoretical calculated value thereof are compared with each other, so as to obtain a probable structure of the measured semiconductor device element by using, for example, a simulated annealing, or the like. A process condition in a process for other semiconductor device elements can be corrected by using the results.

Abstract: A Si1−xGex/Si1−yCy short-period superlattice which functions as a single SiGeC layer is formed by alternately growing Si1−xGex layers (0<x<1) and Si1−yCy layers (0<y<1) each having a thickness corresponding to several atomic layers which is small enough to prevent discrete quantization levels from being generated. This provides a SiGeC mixed crystal which is free from Ge—C bonds and has good crystalline quality and thermal stability. The Si1−xGex/Si1−yCy short-period superlattice is fabricated by a method in which Si1−xGex layers and Si1−yCy layers are epitaxially grown alternately, or a method in which a Si/Si1−xGex short-period superlattice is first formed and then C ions are implanted into the superlattice followed by annealing for allowing implanted C ions to migrate to Si layers.

Abstract: In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A crystal growing apparatus comprises a vacuum vessel, a heating lamp, a lamp controller for controlling the heating lamp, a gas inlet port, a flow rate adjuster for adjusting the flow rate of a gas, a pyrometer for measuring the temperature of a substrate, and a gas supply unit for supplying a Si2H6 gas or the like to the vacuum vessel. An apparatus for ellipsometric measurement comprises: a light source, a polariscope, a modulator, an analyzer, a spectroscope/detector unit, and an analysis control unit for calculating &PSgr;, &Dgr;. In removing a chemical oxide film on the substrate therefrom, in-situ ellipsometric measurement allows a discrimination between a phase 1 during which a surface of the substrate is covered with the oxide film and a phase 2 during which the surface of the substrate is partially exposed so that the supply of gas suitable for the individual phases is performed and halted.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A brake mechanism including a brake member, an urging force switching member pivotable and movable among a plurality of specified positions, and a single elastic member arranged between the brake member and the urging force switching member. By switching one of the action positions of the urging force switching member to another, a different urging force is applied to the brake member from the single elastic member according to the action positions. A drive and control member separately performs a switch-over between the pressing position and the releasing position of the brake member and a switch-over of one of the action positions of the urging force switching member to another.

Abstract: In a tape player configured to wind a tape pulled out of a cassette onto a rotary head to play the tape, a tension mechanism includes a mode member to control the position of a tension control member according to a selected tape mode so as to establish relative contact between a tension member and a tape under a constant pressure in a play mode and separate them in a stop mode.

Abstract: A cassette holder mechanism includes right and left cassette holders independently supporting opposite side marginal portions of a cassette and having guide rollers inserted in guide holes of right and left chassis side walls. Each cassette holder includes a gap at its side portion which engages guide shafts attached to each chassis side wall.

Abstract: Disclosed is a braking mechanism for use in a magnetic recording apparatus essentially comprising a single cam gear and a brake-releasing member. The cam gear and the brake releasing member are so operatively connected that a stepwise rotation of the cam puts selected brake releasers in different brake releasing positions. Specifically in the first releasing position only the supply reel of the apparatus can rotate freely; in the second releasing position the take-up reel of the apparatus can rotate freely, and the supply reel can rotate against a relatively weak resistance; in the third releasing position the take-up and supply reel brakes can rotate freely together; and in unreleased position the supply and take-up reels cannot rotate.The sequential releasing of selected brakes assures coordination of braking operations appropriate for tape-loading, unloading, quick winding, playing and stopping.

Abstract: A tape player having a rotating drum head such as VTR etc. characterized in that a holder, on which at least a guide roller for the tape is mounted outside of the tape path, is disposed movably between its retreated position, where it doesn't interfere with the loading block and the subblock, and its advanced position, where it fronts on the tape path, and is energized towards its retreated position, that control means controlling the movement of the holder arm towards its advanced position is provided, and that an operating member to operate the control means, after this subblock has passed through a position which is occupied by the guide roller in the advanced position of the holder arm, is disposed on the subblock.

Abstract: A video tape recorder includes a pinch roller mechanism driven by a capstan motor to closely fit to a capstan a tape running from a rotary head. The tape is driven in a selected mode by a reel mechanism driven by a tape loading motor. Different mechanisms and members of the recorder are activated at proper relative timings which are established by a timing control mechanism driven by the capstan motor.