Abstract: Techniques for security vulnerability assessment of security-sensitive circuit designs are described. A placement of security-sensitive components of a design may be based on constraints related to how far apart a relevant set of security-sensitive components are allowed without consuming too much power and how to optimize the placement to minimize electromagnetic side-channel leakage or other security vulnerabilities. In one embodiment, a method may receive data that includes a representation of a design of an IC and may identify security-sensitive components of the design from the data. The method may determine a placement for the design based on constraints on a level of security vulnerabilities of the security-sensitive components and may perform a power simulation for the design based on the placement. The method may generate an assessment of the level of security vulnerabilities of the security-sensitive components based on the power simulation to adjust the placement for the design.

Abstract: Systems, machine readable media and methods are described for analyzing one or more physical systems using techniques that recognize patterns in underlying data and use the patterns to efficiently compute outputs using the patterns to reduce computations. The physical systems can be simulated with an estimation (e.g., an estimated power versus time waveform) that can be efficiently computed and then the estimation can be analyzed to detect patterns in the data. The detected patterns can each be analyzed with, in one embodiment, higher accuracy than the estimation to provide data that can be combined across multiple instances of each pattern to provide a higher accuracy evaluation of the system with a lower computational overhead.

Abstract: Techniques are disclosed for conducting poll-based reviews of various businesses and service providers and searching for the businesses and service providers having at least one review. A search module receives a search inquiry related to one or more reviewees having at least one review from one or more user devices. A filter module determines whether the one or more reviewees is associated with at least one search criteria in the search inquiry in order to identify reviewees that are associated with the received search criteria. Thereafter, the search module populates reviewees meeting the search criteria and displays the reviewees meeting the search criteria in a user interface. A trend analysis module performs a trend analysis for the reviewees meeting the search criteria.

Abstract: Disclosed is a system and method for providing poll-based reviews of various businesses and service providers. In particular, a reviewer provides a review by answering poll-based review questions and/or adding new poll-based review questions to provide the most relevant feedback. The review questions can be ranked in order of relevance and/or importance to each reviewer. The data from the review is summarized and presented so that information related to each reviewee is presented in order of preference to the reviewer. Additionally, the present invention gathers data from each reviewer by using polls to tailor suggestions for new reviewees to the reviewer.

Abstract: Disclosed is a system and method for providing poll-based reviews of various businesses and service providers. In particular, a reviewer provides a review by answering poll-based review questions and/or adding new poll-based review questions to provide the most relevant feedback. The review questions can be ranked in order of relevance and/or importance to each reviewer. The data from the review is summarized and presented so that information related to each reviewee is presented in order of preference to the reviewer. Additionally, the present invention gathers data from each reviewer by using polls to tailor suggestions for new reviewees to the reviewer.

Abstract: Disclosed is a system and method for providing poll-based reviews of various businesses and service providers. In particular, a reviewer provides a review by answering poll-based review questions and/or adding new poll-based review questions to provide the most relevant feedback. The review questions can be ranked in order of relevance and/or importance to each reviewer. The data from the review is summarized and presented so that information related to each reviewee is presented in order of preference to the reviewer. Additionally, the present invention gathers data from each reviewer by using polls to tailor suggestions for new reviewees to the reviewer.

Abstract: Techniques are disclosed for conducting poll-based reviews of various businesses and service providers and searching for the businesses and service providers having at least one review. A search module receives a search inquiry related to one or more reviewees having at least one review from one or more user devices. A filter module determines whether the one or more reviewees is associated with at least one search criteria in the search inquiry in order to identify reviewees that are associated with the received search criteria. Thereafter, the search module populates reviewees meeting the search criteria and displays the reviewees meeting the search criteria in a user interface. A trend analysis module performs a trend analysis for the reviewees meeting the search criteria.

Abstract: Disclosed is a system and method for providing poll-based reviews of various businesses and service providers. In particular, a reviewer provides a review by answering poll-based review questions and/or adding new poll-based review questions to provide the most relevant feedback. The review questions can be ranked in order of relevance and/or importance to each reviewer. The data from the review is summarized and presented so that information related to each reviewee is presented in order of preference to the reviewer. Additionally, the present invention gathers data from each reviewer by using polls to tailor suggestions for new reviewees to the reviewer.

Abstract: A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

Abstract: A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.

Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.

Abstract: A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably, each operation has a single control flow and uses vectors of samples for performing the plurality of operations. Each sample is a value associated with a corner. This method minimizes computational resource and memory usage as well as accelerates the turn around time of multi-corner analysis.

Abstract: A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.

Abstract: A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

Abstract: A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

Abstract: A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.

Abstract: A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably, each operation has a single control flow and uses vectors of samples for performing the plurality of operations. Each sample is a value associated with a corner. This method minimizes computational resource and memory usage as well as accelerates the turn around time of multi-corner analysis.

Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.