Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: A system that determines the performance of an integrated circuit (IC). During operation, the system receives probability distributions for parameters for the IC. Next, the system generates samples of the IC, wherein generating a given sample involves using the probability distribution to assign values to the parameters for components within the IC. The system then calculates output performance metrics for the samples based on the assigned values of the parameters, and uses the calculated output performance metrics to generate a distribution of output performance metrics for the samples.

Abstract: A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation context data generated by the signoff tool to implement changes to the design layout will generally produce appropriate and effective results. By accessing this violation context data from the signoff tool, an implementation tool need not rely on its less accurate implementation analysis to determine the optimal design layout modifications for correcting violations detected by the signoff tool.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A system that determines the performance of an integrated circuit (IC). During operation, the system receives probability distributions for parameters for the IC. Next, the system generates samples of the IC, wherein generating a given sample involves using the probability distribution to assign values to the parameters for components within the IC. The system then calculates output performance metrics for the samples based on the assigned values of the parameters, and uses the calculated output performance metrics to generate a distribution of output performance metrics for the samples.

Abstract: One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies a set of worst-case violating paths using the region-specific derating factors. Next, the system computes path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data and the path properties. Finally, the system identifies zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors.

Abstract: A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation context data generated by the signoff tool to implement changes to the design layout will generally produce appropriate and effective results. By accessing this violation context data from the signoff tool, an implementation tool need not rely on its less accurate implementation analysis to determine the optimal design layout modifications for correcting violations detected by the signoff tool.

Abstract: One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies a set of worst-case violating paths using the region-specific derating factors. Next, the system computes path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data and the path properties. Finally, the system identifies zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors.

Abstract: A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and other operations to be performed by EDA tools.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and other operations to be performed by EDA tools.

Abstract: A customizable instruction-set processor (10) implements complex, time-consuming operations by reconfiguring a portion of an instruction execution unit (34) to perform a group of specific functions in hardware rather than implementing a string of operations in software routines. The instruction execution unit (34) has a non-programmable section (46) and a programmable section (48) that receive an opcode and output control signals for controlling a datapath (16). The datapath (16) has a non-programmable datapath (18) and a programmable datapath (32). The programmable section (48) and the programmable datapath (32) are programmed by the user to provide a customizable instruction-set that controls and adds functionality to the customizable instruction-set processor (10).

Abstract: A computer implemented architectural design method for designing an integrated circuit. An algorithmic description of the behavior of the integrated circuit is created (step 202), from which a register transfer logic (RTL) implementation (400, 500) of the integrated circuit is generated by performing a set of design tasks (steps 204-212). The RTL implementation is modified after performing one of the design tasks by branching to another design task such that the design tasks are performed in any order. Data is stored in a common database (12) which can be edited interactively through one of a plurality of data editors (14-22).

Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

Abstract: A controller structure template (60) and method (10) of using the controller structure template (60) for designing a controller structure is provided. The method includes providing (11) a behavioral specification, scheduling, allocating, and binding the behavioral specification (12), dividing (13) the list of statements into statement blocks, clustering (14) the list of statements from each statement block, mapping (15) each statement block into a control block, and mapping (17) each cluster into a control element. The steps of mapping (15 and 17) are performed using a controller structure template (60), which includes a control element template (62), merging logic circuit (63), detection circuit (64), branching logic (67).

Abstract: A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16).

Abstract: An Hardware Description Language (HDL) description file (12) is updated without requiring complete re-assignment of all tokens associated with the HDL statements. The design information is maintained as attributes assigned to the tokens (14). The tokens map onto a block diagram (16). As part of an update to the HDL text file (34), the tokens are compared to see which ones if any have changed. The text lines are compared from left-to-right and right-to-left searching for changes in the text file and associated changes in token mapping (36, 38). All tokens inclusive between the left-most change and right-most change is considered to be different. New tokens are assigned and mapped into the block diagram for the HDL elements that change (40). The mapping of old tokens are removed from the block diagram (42). The mappings from token that did not change are maintained (44).