Patents by Inventor Kayoko Shibata
Kayoko Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776584Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.Type: GrantFiled: April 5, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventor: Kayoko Shibata
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Publication number: 20230253323Abstract: Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the peripheral region. The one or more wirings are disposed adjacent to the memory array region. One or more power vias of the plurality of power vias are disposed through a wiring of the one or more wirings.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: Kayoko Shibata
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Publication number: 20210225413Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Applicant: Micron Technology, Inc.Inventor: Kayoko Shibata
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Patent number: 11004477Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.Type: GrantFiled: July 31, 2018Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventor: Kayoko Shibata
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Publication number: 20200043530Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.Type: ApplicationFiled: July 31, 2018Publication date: February 6, 2020Applicant: Micron Technology, Inc.Inventor: Kayoko Shibata
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Patent number: 10020289Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.Type: GrantFiled: July 27, 2017Date of Patent: July 10, 2018Assignee: Micron Technology, Inc.Inventor: Kayoko Shibata
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Publication number: 20180005995Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.Type: ApplicationFiled: July 27, 2017Publication date: January 4, 2018Applicant: Micron Technology, Inc.Inventor: Kayoko Shibata
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Patent number: 9761564Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.Type: GrantFiled: June 30, 2016Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventor: Kayoko Shibata
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Patent number: 9640243Abstract: A method is disclosed for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through-lines by receiving selection signals at the first terminals located on a first surface of the semiconductor chip, connecting each first terminal to a selected second terminal located on a second surface of the semiconductor chip where each selected second terminal is not aligned with the first terminal to which it is connected, and generating an internal signal based on a selected one of the received selection signals.Type: GrantFiled: June 1, 2015Date of Patent: May 2, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventors: Kayoko Shibata, Hiroaki Ikeda
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Patent number: 9312209Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n?x switch circuits to connect n?x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.Type: GrantFiled: February 27, 2015Date of Patent: April 12, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Publication number: 20150262645Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Applicant: PS4 LUXCO S.A.R.L.Inventors: Kayoko Shibata, Hiroaki Ikeda
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Publication number: 20150179549Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n?x switch circuits to connect n?x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.Type: ApplicationFiled: February 27, 2015Publication date: June 25, 2015Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Patent number: 9048239Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: GrantFiled: January 14, 2013Date of Patent: June 2, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Kayoko Shibata, Hiroaki Ikeda
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Patent number: 9032350Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.Type: GrantFiled: July 8, 2014Date of Patent: May 12, 2015Assignee: PS4 Luxco S.A.R.L.Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Patent number: 8907463Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: GrantFiled: April 26, 2011Date of Patent: December 9, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Kayoko Shibata, Hiroaki Ikeda
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Publication number: 20140320203Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Patent number: 8847221Abstract: A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.Type: GrantFiled: October 11, 2007Date of Patent: September 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Kayoko Shibata
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Patent number: 8839161Abstract: A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias.Type: GrantFiled: April 29, 2013Date of Patent: September 16, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Patent number: 8735288Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.Type: GrantFiled: November 16, 2013Date of Patent: May 27, 2014Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
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Patent number: 8709871Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.Type: GrantFiled: November 10, 2011Date of Patent: April 29, 2014Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima