Patents by Inventor Kayoko Shibata
Kayoko Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070194455Abstract: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.Type: ApplicationFiled: February 21, 2007Publication date: August 23, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20070132085Abstract: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.Type: ApplicationFiled: December 8, 2006Publication date: June 14, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Kayoko Shibata, Hiroaki Ikeda, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
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Publication number: 20070126105Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.Type: ApplicationFiled: December 6, 2006Publication date: June 7, 2007Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
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Publication number: 20070117317Abstract: In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.Type: ApplicationFiled: November 17, 2006Publication date: May 24, 2007Inventors: Hiroaki Ikeda, Kayoko Shibata, Junji Yamada
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Patent number: 7221614Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.Type: GrantFiled: June 14, 2005Date of Patent: May 22, 2007Assignees: NEC Corporation, Elpida Memory, Inc.Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 7209376Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.Type: GrantFiled: June 14, 2005Date of Patent: April 24, 2007Assignees: NEC Corporation, Elpida Memory, Inc.Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20070081376Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: ApplicationFiled: December 6, 2006Publication date: April 12, 2007Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata
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Patent number: 7161820Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: GrantFiled: July 28, 2003Date of Patent: January 9, 2007Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata
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Publication number: 20070001281Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: ApplicationFiled: June 28, 2006Publication date: January 4, 2007Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20060267212Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: ApplicationFiled: May 5, 2006Publication date: November 30, 2006Inventors: Kayoko Shibata, Hiroaki Ikeda
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Publication number: 20060195734Abstract: A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.Type: ApplicationFiled: February 8, 2006Publication date: August 31, 2006Inventors: Kayoko Shibata, Hiroaki Ikeda
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Patent number: 7051225Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.Type: GrantFiled: April 30, 2003Date of Patent: May 23, 2006Assignee: Elpida Memory Inc.Inventors: Yoji Nishio, Kayoko Shibata, Seiji Funaba
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Patent number: 7016212Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N?1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N?1)×Zeffdimm/N2.Type: GrantFiled: July 29, 2003Date of Patent: March 21, 2006Assignee: Elpida Memory Inc.Inventors: Kayoko Shibata, Yoji Nishio, Seiji Funaba
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Register capable of corresponding to wide frequency band and signal generating method using the same
Patent number: 6986072Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.Type: GrantFiled: July 29, 2002Date of Patent: January 10, 2006Assignees: Elpida Memory, Inc., Hitachi Tohbu Semiconductor, Ltd., Hitachi, Ltd.Inventors: Yoji Nishio, Seiji Funaba, Kayoko Shibata, Toshio Sugano, Hiroaki Ikeda, Takuo Iizuka, Masayuki Sorimachi -
Publication number: 20060001176Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.Type: ApplicationFiled: June 27, 2005Publication date: January 5, 2006Inventors: Muneo Fukaishi, Hideaki Saito, Yasuhiko Hagihara, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20050286334Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.Type: ApplicationFiled: June 14, 2005Publication date: December 29, 2005Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20050285174Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.Type: ApplicationFiled: June 14, 2005Publication date: December 29, 2005Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20050286286Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.Type: ApplicationFiled: June 9, 2005Publication date: December 29, 2005Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 6873533Abstract: A memory module of the unbuffered type with ECC function is employed. Configuration of an internal C/A bus is set to a single T-branch topology. An output impedance of a chipset is maintained substantially constant. A capacitor for cutting high-frequency components of a C/A signal is added on a C/A bus.Type: GrantFiled: December 4, 2002Date of Patent: March 29, 2005Assignee: Elpida Memory, Inc.Inventors: Kayoko Shibata, Yoji Nishio
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Publication number: 20040071040Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: ApplicationFiled: July 28, 2003Publication date: April 15, 2004Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata