Patents by Inventor Kazuaki Kurooka

Kazuaki Kurooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530383
    Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 7, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Yoshihiro Funato
  • Patent number: 10145887
    Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Kurooka, Yasuo Morimoto, Yoshihiro Funato
  • Patent number: 10128861
    Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
  • Publication number: 20180323797
    Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Kazuaki KUROOKA, Yoshihiro FUNATO
  • Publication number: 20180267092
    Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Inventors: Kazuaki KUROOKA, Yasuo MORIMOTO, Yoshihiro FUNATO
  • Publication number: 20180234102
    Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
  • Patent number: 10033397
    Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: July 24, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Yoshihiro Funato
  • Patent number: 10006955
    Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 26, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Kurooka, Yasuo Morimoto, Yoshihiro Funato
  • Patent number: 9960779
    Abstract: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 1, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
  • Publication number: 20180069563
    Abstract: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
  • Patent number: 9838027
    Abstract: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n?1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n?1)-th.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
  • Publication number: 20170272088
    Abstract: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n?1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n?1)-th.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
  • Publication number: 20170205458
    Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 20, 2017
    Inventors: Kazuaki KUROOKA, Yasuo MORIMOTO, Yoshihiro FUNATO
  • Publication number: 20170194979
    Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.
    Type: Application
    Filed: December 6, 2016
    Publication date: July 6, 2017
    Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
  • Patent number: 9698804
    Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
  • Patent number: 9473088
    Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 18, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Toshio Kumamoto, Tomoaki Yoshizawa, Kazuaki Kurooka
  • Publication number: 20160226508
    Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
    Type: Application
    Filed: January 10, 2016
    Publication date: August 4, 2016
    Inventors: Kazuaki KUROOKA, Yoshihiro FUNATO
  • Publication number: 20150357980
    Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiro FUNATO, Toshio KUMAMOTO, Tomoaki YOSHIZAWA, Kazuaki KUROOKA
  • Patent number: 9166541
    Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Toshio Kumamoto, Tomoaki Yoshizawa, Kazuaki Kurooka
  • Publication number: 20140340145
    Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
    Type: Application
    Filed: April 16, 2014
    Publication date: November 20, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiro FUNATO, Toshio KUMAMOTO, Tomoaki YOSHIZAWA, Kazuaki KUROOKA