Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: A trace circuit includes the event control circuit and two trace buffer memories. The event control circuit receives data on a control bus, an address bus, and data a bus and stores the data cyclically and alternately in the two buffer memories. Also, the event control circuit makes the two buffer memories output the stored data cyclically and alternately.

Abstract: A digital-to-analog converting circuit of the invention includes p-channel FETs 13 to 16 that compose a current mirror circuit together with p-channel FETs 11, 22 to 24 causing a constant current to flow; transmission gates 42 to 44 perform control by which the number of transistors to be turned ON in the p-channel FETs 22 to 24 is decreased around a medium value of digital codes, and the number of transistors to be turned ON in the p-channel FETs 22 to 24 is increased around the minimum value and the maximum value of the digital codes; and switches 17 to 20 that output analog currents according to the digital codes into two-split routes.

Abstract: A digital-to-analog converting circuit of the invention includes p-channel FETs 13 to 16 that compose a current mirror circuit together with p-channel FETs 11, 22 to 24 causing a constant current to flow; transmission gates 42 to 44 perform control by which the number of transistors to be turned ON in the p-channel FETs 22 to 24 is decreased around a medium value of digital codes, and the number of transistors to be turned ON in the p-channel FETs 22 to 24 is increased around the minimum value and the maximum value of the digital codes; and switches 17 to 20 that output analog currents according to the digital codes into two-split routes.

Abstract: The trace circuit comprises the event control circuit and tow trace buffer memories. The event control circuit receives data on the control bus, address bus, and data bus and makes the data stored cyclically and alternately in the two buffer memories. Also, the event control circuit makes the two buffer memories output the store data cyclically and alternately.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A hotplug tolerant I/O circuit, which is incorporated in a first device, includes a voltage generator. In a hotplug mode, in which an input signal higher than the power supply voltage is applied from a second device to the first device while the power supply voltage is not applied to the first device, the voltage generator generates a control voltage from the input signal, and supplies it to a transistor in the hotplug tolerant I/O circuit. This makes it possible to solve a problem of a conventional hotplug tolerant I/O circuit in that the transistors in the I/O circuit can be damaged in the hotplug mode.

Abstract: A cascade current Miller circuit includes a plurality of MOS transistors that form a current path (PASS32) through which there is flown a current 1/m times the current flowing through a first pair of cascade current Miller circuits structured by two MOS transistors. Further, there are provided a plurality of MOS transistors that form a current path (PASS33) through which there is flown a current 1/(m*3) times the current flowing through the first pair of cascade current Miller circuits. Further, there are provided a plurality of MOS transistors that form a current path (PASS34) through which there is flown a current 2/(m*3) times the current flowing through the first pair of cascade current Miller circuits.

Abstract: A digital-to-analog conversion circuit includes first and second MOS transistors. The first MOS transistors have different sizes corresponding to bits in received digital data, and apply a weight to an input current by switching and outputting a weighted current. The second MOS transistors also have different sizes corresponding to the bits in the digital data, and apply a weight to a current input to the first MOS transistors that are turned ON by switching. The second MOS transistors apply the weight so that the sum of the currents output from the first MOS transistors has a non-linear characteristic.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.