Patents by Inventor Kazuhiro Hoshino
Kazuhiro Hoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080079827Abstract: A method of processing noise in image data by an image processor having a signal-processing portion converting an image signal from an image sensor into a digital signal and outputting the converted signal as image data for each frame, the image data indicating sets of pixel values each having a brightness at a corresponding one of coordinate points arranged in directions of rows and columns is disclosed. The method includes the steps of: extracting pixel values; deciding pixel value; finding autocorrelation coefficients of pixel values which are less than a first threshold value; and deciding random noise in the image.Type: ApplicationFiled: August 24, 2007Publication date: April 3, 2008Inventors: Kazuhiro Hoshino, Hirofuni Sumi
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Publication number: 20070154692Abstract: An ultrathin copper foil with a carrier not causing blistering at a release layer interface, having a low carrier peeling force, friendly to the environment, and enabling easy peeling of a carrier foil and an ultrathin copper foil even under a high temperature environment and a printed circuit board enabling a stable production quality of a base of a printed circuit board for fine pattern applications using the ultrathin copper foil with the carrier, that is, an ultrathin copper foil with a carrier comprising a carrier foil, a release layer, and an ultrathin copper foil, wherein the release layer is formed by a metal A for retaining a release property and a metal B for facilitating plating of the ultrathin copper foil, a content a of the metal A and a content b of the metal B forming the release layer satisfying an equation: 10?a/(a+b)*100?70 and a printed circuit board prepared by using such an ultrathin copper foil with a carrier.Type: ApplicationFiled: December 14, 2006Publication date: July 5, 2007Applicant: Furukawa Circuit Foil Co., Ltd.Inventors: Yuuji Suzuki, Takami Moteki, Kazuhiro Hoshino, Satoshi Fujisawa, Akira Kawakami
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Publication number: 20070141381Abstract: An ultrathin copper foil with a carrier not causing blistering at a release layer interface, having a low carrier peeling force, friendly to the environment, and enabling easy peeling of a carrier foil and an ultrathin copper foil even under a high temperature environment and a printed circuit board enabling a stable production quality of a base of a printed circuit board for fine pattern applications using the ultrathin copper foil with the carrier, that is, a ultrathin copper foil with a carrier comprising a carrier foil, a diffusion prevention layer, a release layer, and an ultrathin copper foil, wherein the release layer is formed by a metal A for retaining a release property and a metal B for facilitating plating of the ultrathin copper foil, a content a of the metal A and a content b of the metal B forming the release layer satisfying an equation: 10?a/(a+b)*100?70 and a printed circuit board prepared by using such a ultrathin copper foil with a carrier.Type: ApplicationFiled: December 15, 2006Publication date: June 21, 2007Inventors: Yuuji Suzuki, Takami Moteki, Kazuhiro Hoshino, Satoshi Fujisawa, Akira Kawakami
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Publication number: 20070042212Abstract: A copper foil reducing transmission loss at a high frequency and excellent in bond strength with a resin substrate, including at least a granular layer and a columnar layer in its thickness direction, the columnar layer being formed on at least one surface of the granular layer forming the copper foil or the granular layer being formed on at least one surface of the columnar layer forming the copper foil, the relation of the thickness A of the granular layer and the thickness B of the columnar layer in the copper foil being preferably A/(A+B)=40 to 99%, a method of production and apparatus for production for the same, and a high frequency circuit using the same.Type: ApplicationFiled: October 25, 2006Publication date: February 22, 2007Inventors: Takami Moteki, Yuuji Suzuki, Kazuhiro Hoshino, Kensaku Shinozaki, Akira Matsuda
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Patent number: 7175920Abstract: The present invention is to provide an ultra-thin copper foil with a carrier which comprises a release layer, a diffusion preventive layer and a copper electroplating layer laminated in this order, or a diffusion preventive layer, a release layer and a copper electroplating layer laminated in this order on the surface of a carrier foil, wherein a surface of the copper electroplating layer is roughened; a copper-clad laminated board comprising the ultra-thin copper foil with a carrier being laminated on a resin substrate; a printed wiring board comprising the copper-clad laminated board on the ultra-thin copper foil of which is formed a wiring pattern; and a multi-layered printed wiring board which comprising a plural number of the above printed wiring board being laminated.Type: GrantFiled: July 13, 2005Date of Patent: February 13, 2007Assignee: Circuit Foil Japan Co., Ltd.Inventors: Akitoshi Suzuki, Shin Fukuda, Kazuhiro Hoshino, Tadao Nakaoka
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Patent number: 7026059Abstract: The present invention is to provide an ultra-thin copper foil with a carrier which comprises a release layer, a diffusion preventive layer and a copper electroplating layer laminated in this order, or a diffusion preventive layer, a release layer and a copper electroplating layer laminated in this order on the surface of a carrier foil, wherein a surface of the copper electroplating layer is roughened; a copper-clad laminated board comprising the ultra-thin copper foil with a carrier being laminated on a resin substrate; a printed wiring board comprising the copper-clad laminated board on the ultra-thin copper foil of which is formed a wiring pattern; and a multi-layered printed wiring board which comprising a plural number of the above printed wiring board being laminated.Type: GrantFiled: September 17, 2001Date of Patent: April 11, 2006Assignee: Circuit Foil Japan Co., Ltd.Inventors: Akitoshi Suzuki, Shin Fukuda, Kazuhiro Hoshino, Tadao Nakaoka
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Publication number: 20050249927Abstract: The present invention is to provide an ultra-thin copper foil with a carrier which comprises a release layer, a diffusion preventive layer and a copper electroplating layer laminated in this order, or a diffusion preventive layer, a release layer and a copper electroplating layer laminated in this order on the surface of a carrier foil, wherein a surface of the copper electroplating layer is roughened; a copper-clad laminated board comprising the ultra-thin copper foil with a carrier being laminated on a resin substrate; a printed wiring board comprising the copper-clad laminated board on the ultra-thin copper foil of which is formed a wiring pattern; and a multi-layered printed wiring board which comprising a plural number of the above printed wiring board being laminated.Type: ApplicationFiled: July 13, 2005Publication date: November 10, 2005Applicant: CIRCUIT FOIL JAPAN CO., LTD.Inventors: Akitoshi Suzuki, Shin Fukuda, Kazuhiro Hoshino, Tadao Nakaoka
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Publication number: 20050174612Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.Type: ApplicationFiled: April 13, 2005Publication date: August 11, 2005Inventors: Toshinobu Sugiyama, Shinichi Yoshimura, Ryoji Suzuki, Kazuhiro Hoshino
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Publication number: 20050173618Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.Type: ApplicationFiled: February 8, 2005Publication date: August 11, 2005Inventors: Toshinobu Sugiyama, Shinichi Yoshimura, Ryoji Suzuki, Kazuhiro Hoshino
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Publication number: 20050104991Abstract: The method for manufacturing a camera module of the present invention includes forming a bump on each electrode portion of an imaging element. Next, a through hole is formed in a substrate. The imaging element is then mounted on a first side of the substrate having at least one bump such that a light receiving portion of the imaging element receives light via the through-hole of the substrate. A periphery of the imaging element is sealed to the substrate. Next, a lens unit is mounted on a second side of the substrate.Type: ApplicationFiled: December 2, 2004Publication date: May 19, 2005Inventors: Kazuhiro Hoshino, Hirofumi Sumi, Kazuya Yonemoto
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Patent number: 6858827Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.Type: GrantFiled: September 18, 2002Date of Patent: February 22, 2005Assignee: Sony CorporationInventors: Toshinobu Sugiyama, Shinichi Yoshimura, Ryoji Suzuki, Kazuhiro Hoshino
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Publication number: 20050019599Abstract: A copper foil reducing transmission loss at a high frequency and excellent in bond strength with a resin substrate, including at least a granular layer and a columnar layer in its thickness direction, the columnar layer being formed on at least one surface of the granular layer forming the copper foil or the granular layer being formed on at least one surface of the columnar layer forming the copper foil, the relation of the thickness A of the granular layer and the thickness B of the columnar layer in the copper foil being preferably A/(A+B)=40 to 99%, a method of production and apparatus for production for the same, and a high frequency circuit using the same.Type: ApplicationFiled: February 2, 2004Publication date: January 27, 2005Inventors: Takami Moteki, Yuuji Suzuki, Kazuhiro Hoshino, Kensaku Shinozaki, Akira Matsuda
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Patent number: 6759642Abstract: A camera module including a light-transmissible board having an infrared rays cutting function on one surface of which a wiring pattern is formed, an image pickup element having a photodetecting portion which is flip-chip-mounted on the same surface of the light-transmissible board while the photodetecting portion is opposite to an area where there is no wiring-pattern, and a lens unit which is mounted on the other surface of the light-transmissible board so as to be located above the photodetecting portion of the image pickup element.Type: GrantFiled: January 23, 2001Date of Patent: July 6, 2004Assignee: Sony CorporationInventor: Kazuhiro Hoshino
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Publication number: 20040038049Abstract: The present invention is to provide an ultra-thin copper foil with a carrier which comprises a release layer, a diffusion preventive layer and a copper electroplating layer laminated in this order, or a diffusion preventive layer, a release layer and a copper electroplating layer laminated in this order on the surface of a carrier foil, wherein a surface of the copper electroplating layer is roughened; a copper-clad laminated board comprising the ultra-thin copper foil with a carrier being laminated on a resin substrate; a printed wiring board comprising the copper-clad laminated board on the ultra-thin copper foil of which is formed a wiring pattern; and a multi-layered printed wiring board which comprising a plural number of the above printed wiring board being laminated.Type: ApplicationFiled: March 20, 2003Publication date: February 26, 2004Applicant: CIRCUIT FOIL JAPAN CO., LTD.Inventors: Akitoshi Suzuki, Shin Fukuda, Kazuhiro Hoshino, Tadao Nakaoka
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Publication number: 20030052252Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.Type: ApplicationFiled: September 18, 2002Publication date: March 20, 2003Inventors: Toshinobu Sugiyama, Shinichi Yoshimura, Ryoji Suzuki, Kazuhiro Hoshino
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Patent number: 6395627Abstract: A semiconductor device comprising a substrate; a first metal wiring formed in the substrate, wherein the first metal wiring is comprised of a metal; an insulating film formed on the substrate so as to cover the first metal wiring; a trench formed in the insulating film; a via hole formed in the insulating film so as to reach the first metal wiring from the trench; a metal plug for plugging the via hole, wherein the metal plug is comprised of the same metal as that for the first metal wiring and formed so as to directly connect to the first metal wiring and reach the inside of the trench; and a second metal wiring formed in the trench so as to directly connect to the metal plug, wherein the second metal wiring is comprised of the same metal as that for the metal plug. The semiconductor device of the present invention is advantageous not only in that is has an improved electromigration resistance, but also in that it has a wiring structure such that the reliability is high and the resistivity is low.Type: GrantFiled: October 19, 2000Date of Patent: May 28, 2002Assignee: Sony CorporationInventors: Kazuhiro Hoshino, Takeshi Nogami
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Publication number: 20010030276Abstract: A camera module including a light-transmissible board 10 having infrared rays cutting function on one surface of which a wiring pattern 13 is formed, an image pickup element 11 having a photodetecting portion 15 which is flip-chip-mounted on the same surface of the light-transmissible board 10 while the photodetecting portion 15 is opposite to an area where there is no wiring-pattern 13, and a lens unit 12 which is mounted on the other surface of the light-transmissible board 10 so as to be located above the photodetecting portion 15 of the image pickup element 11.Type: ApplicationFiled: January 23, 2001Publication date: October 18, 2001Inventor: Kazuhiro Hoshino
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Patent number: 6265310Abstract: A method of manufacturing a semiconductor device utilizing a multi-chamber apparatus comprises the steps of forming a metal film on an insulating layer under the lower pressure within a film forming apparatus and reflowing the metal film on the insulating film, after transferring the semiconductor substrate to a reflow apparatus from the film forming apparatus under the vacuum atmosphere of 1.3×10−6 Pa or less, by simultaneously heating a plurality of semiconductor substrates under the vacuum atmosphere of 1.3×10−6 Pa or less.Type: GrantFiled: June 16, 1998Date of Patent: July 24, 2001Assignee: Sony CorporationInventor: Kazuhiro Hoshino
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Patent number: 6114764Abstract: A semiconductor device, comprising: an insulating layer formed on a semiconductor body; a barrier metal layer comprising titanium nitride formed on the insulating layer; and a n aluminum based alloy layer formed on the barrier metal layer, provided that the aluminum based alloy crystals constituting the aluminum based alloy layer have the crystallographic <111> axis thereof inclined by an angle of from 0 to 5 degrees with respect to the normal of the barrier metal layer on the insulating layer. Also claimed is a process for fabricating the semiconductor device.Type: GrantFiled: November 12, 1996Date of Patent: September 5, 2000Assignee: Sony CorporationInventors: Kazuhiro Hoshino, Takaaki Miyamoto
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Patent number: 6111318Abstract: A wiring layer 17' of a semiconductor device is formed, at first, by forming a Cu--Ta film 15 by adding 0.5 weight % of Ta in Cu on a barrier metal layer, and then, by forming a cap metal layer on the film 15. The wiring layer 17' is then etched with a high temperature RIE method. After this, the wiring layer 17' is heat-treated at about 450 .degree. C. for about 120 minutes in a hydrogen reduction atmosphere. With this heat treatment, Ta is precipitated at the grain boundaries of Cu of the Cu--Ta layer 15. Since Ta does not tend to be alloyed with Cu easily and has low solid solubility in Cu crystal, Ta is precipitated at the grain boundaries of Cu by the above heat treatment. When Ta is precipitated at the grain boundaries of Cu such way, grain boundary diffusion is suppressed to generate less voids, so that the resistance to EM is improved.Type: GrantFiled: January 20, 1998Date of Patent: August 29, 2000Assignee: Sony CorporationInventor: Kazuhiro Hoshino