Patents by Inventor Kazuhiro Nakajima

Kazuhiro Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140182775
    Abstract: A manufacturing method of a structure includes providing a stack of a first material layer to be a part of the structure and a restricting member wherein the first material layer is provided on a surface of the structure in the process of formation, and a part of the restricting member is provided on a surface of the first material layer in reverse of the surface of the structure in the process of formation, providing a support member between the restricting member and the surface of the structure in the process of formation, removing the restricting member, and providing a second material layer to be a part of the structure on surfaces of the first material layer and the support member exposed by removing the restricting member.
    Type: Application
    Filed: June 17, 2013
    Publication date: July 3, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroshi Taniuchi, Kazuhiro Nakajima
  • Patent number: 8673429
    Abstract: The transparent conductive film of the present invention is a transparent conductive film, comprising a transparent film substrate, and a first transparent dielectric layer, a second transparent dielectric layer and a transparent conductive layer that are formed on one or both sides of the transparent film substrate in this order from the transparent film substrate side, wherein the transparent conductive layer is patterned, the relation n2<n3<n1 is satisfied, wherein n1 is the refractive index of the first transparent dielectric layer, n2 is the refractive index of the second transparent dielectric layer, and n3 is the refractive index of the transparent conductive layer, the first transparent dielectric layer has a thickness of from 2 nm to less than 10 nm, the second transparent dielectric layer has a thickness of from 20 nm to 55 nm, and the transparent conductive layer has a thickness of from 15 nm to 30 nm.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 18, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Tomotake Nashiki, Kazuhiro Nakajima, Hideo Sugawara
  • Publication number: 20130258570
    Abstract: A capacitive touch sensor laminate for use in a display panel device includes: a dielectric central substrate structure made of a transparent resin material and formed to have flat surfaces, respectively, on opposite sides thereof; a at least one-layer structured coat layer made of a transparent material, formed on each of the flat surfaces, and including at least one refractive index adjusting layer for suppressing visibility of an electrode pattern formed by the transparent electrically conductive layer; and a transparent electrically conductive layer formed on and in adjacent relation to the coat layer. The at least one-layer structured coat layers formed on respective ones of the flat surfaces are configured such that thicknesses of corresponding layers therein on respective opposite sides of the dielectric central substrate structure are set to allow the corresponding layers to become mutually symmetrical across the dielectric central substrate structure.
    Type: Application
    Filed: November 30, 2011
    Publication date: October 3, 2013
    Inventors: Masahiro Ooura, Tsuyoshi Chiba, Hideo Sugawara, Kazuhiro Nakajima, Tomotake Nashiki, Mayumi Kishioka, Tomohide Banba
  • Publication number: 20130241689
    Abstract: The present invention provides a transparent conductive film in which occurrence of scratches during sliding is suppressed even when transparent conductive layer forming surfaces are so arranged as to face each other. Provided is a transparent conductive film comprising a transparent film base; at least one dielectric layer formed on a first main surface of the transparent film base; and a transparent conductive layer formed on the dielectric layer, wherein the transparent conductive layer is patterned; and the surface on the first main surface of the transparent conductive film has an arithmetical mean roughness Ra of 22 nm or more, and has 140/mm2 or more of protrusions having heights of 250 nm or higher at a pattern-opening part in which the transparent conductive layer is not formed.
    Type: Application
    Filed: December 1, 2011
    Publication date: September 19, 2013
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kazuhiro Nakajima, Tomotake Nashiki, Hideo Sugawara
  • Patent number: 8530041
    Abstract: The transparent conductive film of the present invention is a transparent conductive film, comprising a transparent film substrate, and a first transparent dielectric layer, a second transparent dielectric layer and a patterned transparent conductive layer that are formed on one or both sides of the transparent film substrate in this order from the transparent film substrate side, wherein the transparent conductive layer has a thickness of 31 nm or more, the first transparent dielectric layer has a thickness of from 7 nm to 16 nm, the second transparent dielectric layer has a thickness of from 30 nm to 60 nm, and the relation n2<n3?n1 is satisfied, wherein n1 is the refractive index of the first transparent dielectric layer, n2 is the refractive index of the second transparent dielectric layer, and n3 is the refractive index of the transparent conductive layer.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 10, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kazuhiro Nakajima, Tomotake Nashiki, Hideo Sugawara
  • Publication number: 20120181063
    Abstract: The present invention relates to a transparent conductive film in which a transparent conductive layer is patterned and that is capable of suppressing deterioration of the appearance due to the difference in hues of reflected light between the pattern portion and the portion directly under the pattern opening portion, and a touch panel that uses it. In the transparent conductive film (10) of the present invention, a first transparent dielectric layer (2) and a transparent conductive layer (4) are formed on a transparent base material (1) in this order. It is preferable that a relationship 0?|a*P?a*O|?4.00 is satisfied and a relationship 0?|b*P?b*O|?5.00 is satisfied where a hue a* value and a hue b* value of reflected light when the pattern portion (P) is irradiated with white light are a*P and b*P, respectively, and a hue a* value and a hue b* value of reflected light when a portion directly under the pattern opening portion (O) is irradiated with white light are a*O and b*O, respectively.
    Type: Application
    Filed: September 28, 2010
    Publication date: July 19, 2012
    Applicant: Nitto Denko Corporation
    Inventors: Kazuhiro Nakajima, Hideo Sugawara, Tomotake Nashiki
  • Publication number: 20120114919
    Abstract: The present invention provides a transparent conductive film in which the difference in visibility between the pattern portion and the pattern opening portion is kept small even when a transparent conductive layer is patterned. The transparent conductive film has a first dielectric layer, a second dielectric layer, and a transparent conductive layer in this order on a transparent film substrate, a thickness d21 of the first dielectric layer is larger than a thickness d22 of the second dielectric layer, the thickness d21 of the first dielectric layer is 8 to 40 nm and the thickness d22 of the second dielectric layer is 5 to 25 nm, and a difference between the thickness d21 of the first dielectric layer and the thickness d22 of the second dielectric layer, d21-d22, is 3 to 30 nm.
    Type: Application
    Filed: October 12, 2011
    Publication date: May 10, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kazuhiro Nakajima, Tomotake Nashiki, Hideo Sugawara
  • Patent number: 7924458
    Abstract: An object of the present invention is to provide a method for manufacturing a three-dimensional object which method is able to easily manufacture a three-dimensional object using a low-cost apparatus. The present invention thus manufactures a three-dimensional object containing a three-dimensional image by printing a two-dimensional image on print media each having at least an ink receiving layer and a bonding layer, on the basis of an ink jet scheme, and stacking the print media on which the two-dimensional image is printed so that the print media are bonded together via the bonding layers.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Taniuchi, Akihiro Mouri, Koichiro Nakazawa, Kazuhiro Nakajima
  • Publication number: 20100013798
    Abstract: The transparent conductive film of the present invention is a transparent conductive film, comprising: a transparent film substrate; a patterned transparent conductive layer formed on one side of the transparent film substrate; and a colored layer provided on at least one of an opposite side of the transparent conductive layer from the transparent film substrate and an opposite side of the transparent film substrate from the transparent conductive layer, wherein the colored layer has an average absorptance of from 35% to 90% for light in the wavelength range of from 380 nm to 780 nm.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kazuhiro Nakajima, Tomotake Nashiki, Hideo Sugawara
  • Publication number: 20100013784
    Abstract: The transparent conductive film of the present invention is a transparent conductive film, comprising a transparent film substrate, and a first transparent dielectric layer, a second transparent dielectric layer and a transparent conductive layer that are formed on one or both sides of the transparent film substrate in this order from the transparent film substrate side, wherein the transparent conductive layer is patterned, the relation n2<n3<n1 is satisfied, wherein n1 is the refractive index of the first transparent dielectric layer, n2 is the refractive index of the second transparent dielectric layer, and n3 is the refractive index of the transparent conductive layer, the first transparent dielectric layer has a thickness of from 2 nm to less than 10 nm, the second transparent dielectric layer has a thickness of from 20 nm to 55 nm, and the transparent conductive layer has a thickness of from 15 nm to 30 nm.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 21, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventors: Tomotake Nashiki, Kazuhiro Nakajima, Hideo Sugawara
  • Publication number: 20100015417
    Abstract: The transparent conductive film of the present invention is a transparent conductive film, comprising a transparent film substrate, and a first transparent dielectric layer, a second transparent dielectric layer and a patterned transparent conductive layer that are formed on one or both sides of the transparent film substrate in this order from the transparent film substrate side, wherein the transparent conductive layer has a thickness of 31 nm or more, the first transparent dielectric layer has a thickness of from 7 nm to 16 nm, the second transparent dielectric layer has a thickness of from 30 nm to 60 nm, and the relation n2<n3?n1 is satisfied, wherein n1 is the refractive index of the first transparent dielectric layer, n2 is the refractive index of the second transparent dielectric layer, and n3 is the refractive index of the transparent conductive layer.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 21, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kazuhiro Nakajima, Tomotake Nashiki, Hideo Sugawara
  • Publication number: 20090112463
    Abstract: A navigation device having a route search section for searching for a route from a start point to destination that are specified, a sensor section for detecting traveling conditions of the vehicle, a GPS reception section for positioning a current position, a map storage section having map information stored in it, output means (voice output section), an acceleration determination section, and a rapid-acceleration/deceleration-information recording section.
    Type: Application
    Filed: May 8, 2007
    Publication date: April 30, 2009
    Applicants: SANYO ELECTRIC CO., LTD., SANYO CONSUMER ELECTRONICS CO., LTD.,
    Inventors: Kazuhiro Yamane, Kazuhiro Nakajima, Shunsuke Tsutsumi, Yuichi Abe
  • Patent number: 7311394
    Abstract: A width A of the scanning area of the ink ejection orifices and a width B of the scanning area of the reacting liquid ejection orifices are respectively set as A=(n?a)×p and B=n×p, while amount of the feeding of the printing sheet during each scan corresponds to the width of the scanning area of the reacting liquid ejection orifices, that is, A=(n?a)×p. With this system, the width of the scanning area, wherein ejection of the reacting liquid precedes ejection of the ink, is made shorter by C=a×p than the width of following scanning area; the scanning area having the width C is scanned two times by the row of the ink ejection orifices, and the thinning process is applied to this area having the width C.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: December 25, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takuei Ishikawa, Kazuhiro Nakajima, Koichiro Nakazawa, Katsuhiro Shirota
  • Publication number: 20070146734
    Abstract: An object of the present invention is to provide a method for manufacturing a three-dimensional object which method is able to easily manufacture a three-dimensional object using a low-cost apparatus. The present invention thus manufactures a three-dimensional object containing a three-dimensional image by printing a two-dimensional image on print media each having at least an ink receiving layer and a bonding layer, on the basis of an ink jet scheme, and stacking the print media on which the two-dimensional image is printed so that the print media are bonded together via the bonding layers.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: HIROSHI TANIUCHI, AKIHIRO MOURI, KOICHIRO NAKAZAWA, KAZUHIRO NAKAJIMA
  • Patent number: 7205795
    Abstract: A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: April 17, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Masaharu Mizuno, Kazuhiro Nakajima
  • Publication number: 20060176331
    Abstract: A width A of the scanning area of the ink ejection orifices and a width B of the scanning area of the reacting liquid ejection orifices are respectively set as A =(n?a)×n p and B=n×p, while amount of the feeding of the printing sheet during each scan corresponds to the width of the scanning area of the reacting liquid ejection orifices, that is, A=(n?a)×p. With this system, the width of the scanning area, wherein ejection of the reacting liquid precedes ejection of the ink, is made shorter by C=a×p than the width of following scanning area; the scanning area having the width C is scanned two times by the row of the ink ejection orifices, and the thinning process is applied to this area having the width C.
    Type: Application
    Filed: May 6, 2004
    Publication date: August 10, 2006
    Applicant: Canon Kabushiki Kaisha
    Inventors: Takuei Ishikawa, Kazuhiro Nakajima, Koichiro Nakazawa, Katsuhiro Shirota
  • Patent number: 6958659
    Abstract: A ring oscillator for a test apparatus and method for verifying fabrication of transistors in an integrated circuit on a die under test is implemented. The ring oscillator is fabricated on the die and includes a positive feedback loop between a circuit output terminal and a feedback input terminal. The feedback loop includes a plurality of delaying stages connected in cascade. A transfer gate is coupled to each delaying stage. Each of the transfer gates includes a pair of transistors of the first and second conductivity types connected in parallel. The ring oscillator is operable to provide a first oscillator output signal during a first test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are OFF. The ring oscillator is operable to provide a second oscillator output signal during a second test mode when the transistors of the first conductivity type are OFF and the transistors of the second conductivity type are ON.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: October 25, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Kazuhiro Nakajima
  • Publication number: 20050218936
    Abstract: A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Applicant: NEC Electronics Corporation
    Inventors: Masaharu Mizuno, Kazuhiro Nakajima
  • Patent number: 6946875
    Abstract: A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 20, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Kenji Yamamoto, Masaharu Mizuno, Kazuhiro Nakajima
  • Publication number: 20050098779
    Abstract: In a production process for producing a plurality of semiconductor devices on chip areas which are defined on a wafer, the wafer is processed such that each of the chip areas is produced as a semi-finished semiconductor device by forming a first wiring-arrangement section on each of the chip areas. The wafer is subjected to a provisional yield-rate test in which it is examined whether each of the semi-finished semiconductor devices on the wafer is acceptable or unacceptable to calculate a yield-rate of acceptable semi-finished semiconductor devices. When the wafer passes the provisional yield-rate test, the wafer is further processed such that each of the chip areas is produced as a finished semiconductor device by forming a second wiring-arrangement section on the first wiring-arrangement section.
    Type: Application
    Filed: July 24, 2003
    Publication date: May 12, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kazuhiro Nakajima, Kouji Kanba