Abstract: A power control device includes an electric power storage device connected across a power supply line for a load and including at least one electric double layer capacitor (EDLC) bank and a secondary battery combined with the EDLC bank, the EDLC bank including a plurality of parallel-connected rows of EDLC unit cells, each of the rows including a plurality of series-connected EDLC unit cells, and a control device controlling the electric power storage device so that when an input power to the electric power storage device is interrupted, the EDLC bank supplies electric power to the load for an initial period of the power interrupt and subsequently, the secondary battery supplies electric power to the load.

Abstract: A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Abstract: A ring oscillator for a test apparatus and method for verifying fabrication of transistors in an integrated circuit on a die under test is implemented. The ring oscillator is fabricated on the die and includes a positive feedback loop between a circuit output terminal and a feedback input terminal. The feedback loop includes a plurality of delaying stages connected in cascade. A transfer gate is coupled to each delaying stage. Each of the transfer gates includes a pair of transistors of the first and second conductivity types connected in parallel. The ring oscillator is operable to provide a first oscillator output signal during a first test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are OFF. The ring oscillator is operable to provide a second oscillator output signal during a second test mode when the transistors of the first conductivity type are OFF and the transistors of the second conductivity type are ON.

Abstract: A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.

Abstract: An electrical double-layer capacitor has a construction wherein a pair of positive and negative polarizing electrodes whose chief constituent is active carbon laminated (or coiled) in a condition with a separator sandwiched therebetween and with their outsides held by respective aluminum collection electrodes are accommodated in a case made of metal etc. in a condition impregnated with electrolyte using propylene carbonate as solvent. The polarizing electrodes have a solid-state structure wherein the active carbon particles are the chief constituent (first substance) and these active carbon particles 3 are connected in network fashion by a second substance such as for example nano-size carbon black which is of higher electrical conductivity than the active carbon and of smaller size than the active carbon particles.

Abstract: An output apparatus which produces the print output by saving in a first memory print data input via a two-way interface, and converting the print data into the print out information, comprising a second memory different from the first memory for saving the print data with a print ID number added which is input via the interface, a retrieving unit for retrieving corresponding print data of the second memory based on a print ID number input from the outside, and an output unit for outputting the retrieved print data converted into the print out information.

Abstract: A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Abstract: A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

Abstract: A data transfer circuit or a recording apparatus includes an address setting unit for setting a start address for a buffer memory, an offset setting unit for setting an offset for the buffer memory, and an address creating unit for creating a predetermined number of consecutive transfer addresses to be supplied for the buffer memory using a reference address. The circuit also includes an arithmetic logic unit that, after the address creating unit has created transfer addresses using the start address as a reference address, calculates a new reference address in accordance with the offset relative to the start address so as to provide the new reference address to the address creating unit.

Abstract: In a method of designing a signal distribution circuit, a plurality of circuit patterns of buffer circuits and patterns of wiring lines are arranged and connected to have a tree structure. A total delay time from an input of the buffer circuit in the highest layer of the tree structure to an output of each of the buffer circuits in the lowest layer of the tree structure is calculated. Each of the plurality of circuit patterns of the buffer circuits is selectively substituted by one of substitution patterns of substitution buffer circuits such that the total delay times fall within a predetermined range. All the outputs of the buffer circuits in the lowest layer of the tree structure are connected.

Abstract: In a semiconductor integrated circuit design method in which a circuit is artificially (preliminarily) configured by carrying out layout and wirings of each of sequential circuits and combinational circuits, and timing specifications of the sequential circuits are checked based on a simulation which confirms the operation of the circuit, several blocks of sequential circuits of the same type with different setup time and hold time and having the same function, block size, terminal number, terminal positions and wiring inhibition information are prepared in advance, a simulation is executed by artificially configuring a semiconductor integrated circuit by layout of each block and wirings between blocks, and the simulation is continued while replacing the arranged sequential circuits by sequential circuits of the same type, until the number of sequential circuits for which clock signal undergoes a change within a prescribed time ceases to decrease, and the margins of the timing specifications stops to increase

Abstract: A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.

Abstract: Methods of designing and manufacturing a semiconductor device are disclosed in order to reduce the manufacturing cost of the semiconductor device, and to easily realize a high-speed circuit by reducing wiring capacity. A maximum pitch of wiring of the wiring layers is determined under a condition that power consumption of the semiconductor chips at a predetermined operating frequency is equal to or less than a predetermined value, and the width and spacing of wiring of the wiring layers and the width of each contact for mounting the semiconductor chips are determined based on the determined wiring pitch the semiconductor device is manufactured by using a mask and a manufacturing process by which the determined pitch and width of wiring are realized.

Abstract: A liquid jet recording method includes applying thermal energy to liquid in a liquid passage to produce film boiling of the liquid to produce a. bubble; permitting the bubble to communicate with ambience; wherein the liquid passage is not blocked in the communicating step.

Abstract: A liquid jet recording method using thermal energy to eject liquid from a liquid passage through an ejection outlet, the liquid passage being provided with a heat generating resistor, wherein at least one of the following conditions is satisfied: 0.1≦H/L≦0.9 R/L≧0.5 &phgr;/Wn≦1.0 S/Sh≦3.0 where L is a distance between the heat generating resistor and the ejection outlet, H is a height of the liquid passage, R is a maximum diameter of the ejection outlet, &phgr; is a converted diameter of the ejection outlet, Wn is a passage width of a portion where the heat generating resistor is disposed, S is an area of the ejection outlet, and Sh is an area of the. heat generating resistor; wherein a bubble created by heat generating resistor communicates with ambience.

Abstract: A power control device includes an electric power storage device connected across a power supply line for a load. The electric power storage device includes an electric double layer capacitor (EDLC) bank including a plurality of parallel-connected rows of EDLC unit cells, each of which rows includes a plurality of series-connected EDLC unit cells.

Abstract: A data transfer circuit or a recording apparatus includes an address setting unit for setting a start address for a buffer memory, an offset setting unit for setting an offset for the buffer memory, and an address creating unit for creating a predetermined number of consecutive transfer addresses to be supplied for the buffer memory using a reference address. The circuit also includes an arithmetic logic unit that, after the address creating unit has created transfer addresses using the start address as a reference address, calculates a new reference address in accordance with the offset relative to the start address so as to provide the new reference address to the address creating unit.

Abstract: A liquid jet recording method using thermal energy to eject liquid from a liquid passage through an ejection outlet, the liquid passage being provided with a heat generating resistor, wherein at least one of the following conditions is satisfied:

Abstract: Methods of designing and manufacturing a semiconductor device are disclosed in order to reduce the manufacturing cost of the semiconductor device, and to easily realize a high-speed circuit by reducing wiring capacity. A maximum pitch of wiring of the wiring layers is determined under a condition that power consumption of the semiconductor chips at a predetermined operating frequency is equal to or less than a predetermined value, and the width and spacing of wiring of the wiring layers and the width of each contact for mounting the semiconductor chips are determined based on the determined wiring pitch. the semiconductor device is manufactured by using a mask and a manufacturing process by which the determined pitch and width of wiring are realized.

Abstract: An output apparatus which produces the print output by saving in a first memory print data input via a two-way interface, and converting the print data into the print out information, comprising a second memory different from the first memory for saving the print data with a print ID number added which is input via the interface, a retrieving unit for retrieving corresponding print data of the second memory based on a print ID number input from the outside, and an output unit for outputting the retrieved print data converted into the print out information.