Patents by Inventor Kazuhiro Shimizu
Kazuhiro Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110316115Abstract: A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type caType: ApplicationFiled: February 1, 2011Publication date: December 29, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazuhiro SHIMIZU
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Patent number: 8084802Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: February 11, 2011Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 8045658Abstract: A reception apparatus includes: an extraction section; a transmission line characteristic estimation section; an estimation section; a frequency shift amount production section; a control section; an addition section; a first frequency shifting section; a second frequency shifting section; an interpolation section; a compensation section; a detection section; and an operation section.Type: GrantFiled: October 28, 2008Date of Patent: October 25, 2011Assignee: Sony CorporationInventors: Hidetoshi Kawauchi, Tadaaki Yuba, Tamotsu Ikeda, Koji Naniwada, Kazuhiro Shimizu, Lachlan Bruce Michael
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Patent number: 8044487Abstract: A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.Type: GrantFiled: December 15, 2006Date of Patent: October 25, 2011Assignee: Mitsubishi Electric CorporationInventors: Satoshi Rittaku, Kazuhiro Shimizu
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Patent number: 8045945Abstract: A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.Type: GrantFiled: February 26, 2009Date of Patent: October 25, 2011Assignee: Sony CorporationInventors: Hidetoshi Kawauchi, Tadaaki Yuba, Toshiyuki Miyauchi, Takashi Yokokawa, Takuya Okamoto, Tamotsu Ikeda, Koji Naniwada, Kazuhiro Shimizu, Lachlan Bruce Michael
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Publication number: 20110254049Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: ApplicationFiled: June 14, 2011Publication date: October 20, 2011Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazuhiro SHIMIZU, Hajime AKIYAMA, Naoki YASUDA
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Publication number: 20110204426Abstract: According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film.Type: ApplicationFiled: August 30, 2010Publication date: August 25, 2011Inventors: Shoko KIKUCHI, Takafumi IKEDA, Kazuhiro SHIMIZU
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Patent number: 7977787Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: GrantFiled: December 11, 2008Date of Patent: July 12, 2011Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Patent number: 7963030Abstract: Disclosed is a multilayer wiring board in which a copper foil is bonded by a thermocompression bonding onto an insulating layer having a bump for interlayer connection buried therein, and the copper foil and the bump are electrically connected to each other. The copper foil is provided with an oxide film having a thickness of 50 ? to 350 ? on a surface in contact with the bump and an insulating layer. In a manufacturing process, for example, an oxide coating of the copper foil to be subject to the thermocompression bonding is removed by acid cleaning, and then an oxide film having an appropriate thickness is formed by irradiating the copper foil with ultraviolet light. Consequently, reliability in electrical connection between the copper foil and the burn is adequately ensured, while achieving sufficient mechanical connection strength between the copper foil and the insulating layer.Type: GrantFiled: September 29, 2005Date of Patent: June 21, 2011Assignee: Sony Chemical & Information Device CorporationInventors: Kazuhiro Shimizu, Mitsuyuki Takayasu, Kiyoe Nagai
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Publication number: 20110134700Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: February 11, 2011Publication date: June 9, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20110108906Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.Type: ApplicationFiled: January 18, 2011Publication date: May 12, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Toshitake YAEGASHI, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20110073932Abstract: A non volatile semiconductor memory device includes: a semiconductor substrate comprising element regions; gate structures each comprising a first gate insulation film, a charge storage layer, a second gate insulation film, and a control gate; element isolation insulation films defining the element regions and electrically isolating the element regions; impurity diffusion layers in the element regions; a third gate insulation film of a first insulation material located between the gate structures; and a fourth gate insulation film of a second insulation material which is different from the first insulation material configured to be in contact with side walls of the gate structures. A bottom face of the fourth gate insulation film is located so as to be remote from a surface of the semiconductor substrate by a distance equal to at least half of a height of the charge storage layer.Type: ApplicationFiled: March 16, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Shimizu, Hideto Horii
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Patent number: 7893477Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: July 27, 2007Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20110038385Abstract: Disclosed herein is a signal processing apparatus including a first detection block; a second detection block; a duration detection block; a duration information output block; and a demodulation block.Type: ApplicationFiled: August 6, 2010Publication date: February 17, 2011Inventors: Kazuhiro SHIMIZU, Takashi Yokokawa, John Wilson, Samuel Atungsiri
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Patent number: 7888728Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.Type: GrantFiled: June 17, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20100309722Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20100309723Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20100283116Abstract: A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad.Type: ApplicationFiled: December 24, 2009Publication date: November 11, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazuhiro SHIMIZU
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Patent number: 7786525Abstract: A nonvolatile semiconductor memory device includes an element isolation insulating film buried in first trenches, a floating gate electrode formed on an element forming region with a first gate insulating film being interposed between them, and a second gate insulating film formed on upper portions of the floating gate electrode and an element isolation insulating film. The floating gate electrode is formed so as to have a side that extends from a bottom thereof to its upper portion and is substantially an extension of a sidewall of each first trench. The element isolation insulating film includes a portion located between its sidewall and the sidewall of a second trench, and the portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate. The film thickness is equal to a film thickness of the second gate insulating film.Type: GrantFiled: April 17, 2008Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuhiro Shimizu
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Patent number: 7787277Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: March 21, 2008Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome