Abstract: A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region having a level shift wire region that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

Abstract: Extending from an upper surface of an n? semiconductor layer on a p? semiconductor substrate to the interface between the n? semiconductor layer and the p? semiconductor substrate, a p+ impurity region is provided. The p+ impurity region defines a high-potential island region, a low-potential island region and a slit region in the n? semiconductor layer. The n? semiconductor layer in the high-potential island region and the n? semiconductor layer in the low-potential island region are connected by the n? semiconductor layer in the slit region, and a logic circuit is formed in the n? semiconductor layer in the high-potential island region. A width in the direction of Y axis of the n? semiconductor layer in the slit region is set to be narrower than a width in the direction of the Y axis of the n? semiconductor layer in the high-potential island region.

Abstract: An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.

Abstract: Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

Abstract: Disclosed is a multilayer wiring board in which a copper foil is bonded by a thermocompression bonding onto an insulating layer having a bump for interlayer connection buried therein, and the copper foil and the bump are electrically connected to each other. The copper foil is provided with an oxide film having a thickness of 50 ? to 350 ? on a surface in contact with the bump and an insulating layer. In a manufacturing process, for example, an oxide coating of the copper foil to be subject to the thermocompression bonding is removed by acid cleaning, and then an oxide film having an appropriate thickness is formed by irradiating the copper foil with ultraviolet light. Consequently, reliability in electrical connection between the copper foil and the burn is adequately ensured, while achieving sufficient mechanical connection strength between the copper foil and the insulating layer.

Abstract: A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region having a level shift wire region that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

Abstract: A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.

Abstract: A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the high-potential-side logic circuit (301) is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region (405) having a level shift wire region (404) that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

Abstract: First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A reception apparatus includes: an extraction section; a transmission line characteristic estimation section; an estimation section; a frequency shift amount production section; a control section; an addition section; a first frequency shifting section; a second frequency shifting section; an interpolation section; a compensation section; a detection section; and an operation section.

Abstract: A drive circuit for driving a power device has a level shift circuit which level-shifts an ON signal and an OFF signal for controlling the power device in ON and OFF states, respectively, and which outputs the level-shifted ON and OFF signals, a mask circuit which stops transmission of the ON and OFF signals when both the ON and OFF signals are lower than a first threshold level, and a short circuit which is provided in a stage before the mask circuit, and which short-circuits a path for transmission of the ON signal and a path for transmission of the OFF signal when both the ON and OFF signals are lower than a second threshold level. The second threshold level is higher than the first threshold level.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: The present invention provides a novel solid powder which has transparency in its appearance, and has excellent usability and, in addition, excellent feeling of use such as dry feeling and fresh light feeling without sticky feeling during application. It is achieved by a solid powder cosmetic comprising: (A) 25 to 55% by mass of elastic powder mixture; (B) 20 to 40% by mass of non-elastic spherical silicone resin powder with an average particle diameter within the range of 0.1 to 50 ?m; and (C) 25 to 55% by mass of oil, as essential components, wherein (A) the elastic powder mixture comprises one or more types of each (A1) an elastic powder and (A2) a composite powder obtained by coating the periphery of an elastic powder with a non-elastic material, said solid powder cosmetic being obtained by caking a mixed composition of these essential components.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which ejects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a first trench, an element isolation insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode. The element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode. The floating gate electrode includes a sidewall further including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed between them. The control gate electrode is buried in the second trench with the second gate insulating film being interposed between them.

Abstract: A p impurity region (3) defines a RESURF isolation region in an n? semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n? semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n? semiconductor layer (2) and a p? semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.