Patents by Inventor Kazumi Watase
Kazumi Watase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7964475Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.Type: GrantFiled: December 6, 2007Date of Patent: June 21, 2011Assignee: Panasonic CorporationInventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase
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Patent number: 7622792Abstract: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.Type: GrantFiled: December 8, 2006Date of Patent: November 24, 2009Assignee: Panasonic CorporationInventors: Kazumi Watase, Tsuyoshi Hamatani
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Patent number: 7595557Abstract: A metal wire for inspection and an electrode for inspection are formed on a region of a semiconductor substrate where a metal wire and an electrode for external connection are not formed. The metal wire for inspection and the electrode for inspection electrically detect an open failure, a short-circuit failure and a leakage failure of the metal wire and a connection failure between an element electrode and the metal wire. A semiconductor wafer is subjected to an electrical test, so that it is possible to detect the aforementioned failures with good accuracy during a manufacturing process.Type: GrantFiled: June 16, 2006Date of Patent: September 29, 2009Assignee: Panasonic CorporationInventors: Kazumi Watase, Akio Nakamura, Katsumi Ootani
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Publication number: 20080135975Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.Type: ApplicationFiled: December 6, 2007Publication date: June 12, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase
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Patent number: 7279357Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 5, 2005Date of Patent: October 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20070132096Abstract: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.Type: ApplicationFiled: December 8, 2006Publication date: June 14, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Tsuyoshi Hamatani
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Publication number: 20070052106Abstract: A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.Type: ApplicationFiled: November 1, 2004Publication date: March 8, 2007Inventors: Kazumi Watase, Akio Nakamura, Minoru Fujisaku, Hiroki Naraoka, Takahiro Nakano
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Publication number: 20060286689Abstract: A metal wire for inspection and an electrode for inspection are formed on a region of a semiconductor substrate where a metal wire and an electrode for external connection are not formed. The metal wire for inspection and the electrode for inspection electrically detect an open failure, a short-circuit failure and a leakage failure of the metal wire and a connection failure between an element electrode and the metal wire. A semiconductor wafer is subjected to an electrical test, so that it is possible to detect the aforementioned failures with good accuracy during a manufacturing process.Type: ApplicationFiled: June 16, 2006Publication date: December 21, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Akio Nakamura, Katsumi Ootani
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Patent number: 6954001Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: GrantFiled: August 17, 2004Date of Patent: October 11, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Publication number: 20050199979Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: ApplicationFiled: May 5, 2005Publication date: September 15, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Patent number: 6924173Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: March 14, 2003Date of Patent: August 2, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6914331Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 21, 2003Date of Patent: July 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Patent number: 6852616Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: GrantFiled: June 10, 2002Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka
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Publication number: 20050012214Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: ApplicationFiled: August 17, 2004Publication date: January 20, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Patent number: 6784557Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: GrantFiled: December 2, 2002Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Publication number: 20030218247Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: ApplicationFiled: May 21, 2003Publication date: November 27, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20030194834Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: ApplicationFiled: March 14, 2003Publication date: October 16, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Publication number: 20030116867Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: ApplicationFiled: December 2, 2002Publication date: June 26, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Patent number: 6559528Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: February 20, 2001Date of Patent: May 6, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6512298Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: GrantFiled: October 29, 2001Date of Patent: January 28, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka