Patents by Inventor Kazuo Hattori

Kazuo Hattori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180114647
    Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and a large specific surface area; a dielectric layer formed in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The dielectric layer is interposed between the conductive part and the high specific surface area substrate, and the high specific surface area substrate and the second terminal electrode are electrically insulated from each other.
    Type: Application
    Filed: December 21, 2017
    Publication date: April 26, 2018
    Inventors: Noriyuki Inoue, Kazuo Hattori, Hiromasa Saeki
  • Publication number: 20180114640
    Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and has a large specific surface area; a dielectric layer in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The element main body includes a first region that contributes to the acquisition of the capacitance and second regions having a smaller void ratio than the first region. The second regions have a void ratio of 25% or less.
    Type: Application
    Filed: December 21, 2017
    Publication date: April 26, 2018
    Inventors: NORIYUKI INOUE, Kazuo Hattori, Hiromasa Saeki
  • Patent number: 9947466
    Abstract: An electronic component includes an electronic element including outer electrodes on a surface, a substrate terminal on which the electronic element is mounted, and a conductor that covers at least a portion of the substrate terminal. The substrate terminal includes a first main surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface. The substrate terminal includes a mounting electrode that is provided on the first main surface and is electrically connected to the outer electrodes of the electronic element. The mounting electrode includes adjacent portions that are located to be adjacent to the side surface of the substrate terminal. The conductor covers at least a portion of the adjacent portion.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 17, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Hirobumi Adachi
  • Publication number: 20180075975
    Abstract: A composite electronic component includes a capacitor device and a resistor device stacked together in a height direction. The capacitor device includes a capacitor body and first and second external electrodes. The resistor device includes a base, a resistive element, first and second upper surface conductors, first and second lower surface conductors, a first connection conductor, and a second connection conductor. The upper surface of the base of the resistor device faces the lower surface of the capacitor body of the capacitor device, the first upper surface conductor is electrically connected to the first external electrode, and the second upper surface conductor is electrically connected to the second external electrode.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 15, 2018
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Shinichiro KUROIWA
  • Publication number: 20180075974
    Abstract: A composite electronic component includes a capacitor device and a resistor device stacked together in a height direction. The capacitor device includes a capacitor body and first and second external electrodes. The resistor device includes a base, a resistive element, first and second upper surface conductors, first and second lower surface conductors, a first connection conductor, and a second connection conductor. The upper surface of the base of the resistor device faces the lower surface of the capacitor body of the capacitor device, the first upper surface conductor is electrically connected to the first external electrode, and the second upper surface conductor is electrically connected to the second external electrode.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 15, 2018
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Shinichiro KUROIWA
  • Publication number: 20180047517
    Abstract: A capacitor that includes a conductive metal base material with a porous part, a dielectric layer on the porous part, and an upper electrode on the dielectric layer, and has an electrostatic capacitance formation part only on one principal surface side of the capacitor.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 15, 2018
    Inventors: KOICHI KANRYO, Noriyuki Inoue, Hiromasa Saeki, Takeo Arakawa, Kazuo Hattori, Ken Ito
  • Patent number: 9867278
    Abstract: Laminated ceramic capacitors include ceramic layers and inner electrodes that are alternately laminated. The inner electrodes are laminated in the same lamination direction, and a first outer electrode and a second outer electrode are electrically connected to the inner electrodes. In a mounting process, the laminated ceramic capacitors are mounted on a mounting surface such that the inner electrodes are perpendicular or substantially perpendicular to the mounting surface.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Toshiki Tanaka
  • Patent number: 9832877
    Abstract: A collective substrate for resistor devices includes a base, a first conductive pattern in a to-be-product region and a to-be-cut-away region of the base, and a resistive element in the to-be-product region of the base. The to-be-cut-away region includes a first region adjacent to the to-be-product region in a first direction, and a second region adjacent to the to-be-product region in a second direction. The first conductive pattern includes a first terminal portion connected to the resistive element and disposed in the to-be-product region, a first electrode portion disposed in the first region and larger in area than the first terminal portion, and a first interconnect portion extended from the first terminal portion toward the second region to be connected to the first electrode portion.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 28, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Shinichiro Kuroiwa
  • Publication number: 20170339792
    Abstract: A circuit module includes a first and second monolithic ceramic capacitors encapsulated by a mold resin layer on a wiring board. The first and second monolithic ceramic capacitors are lined up along a direction parallel or substantially parallel to the main surface of the wiring board and are electrically connected in series or in parallel through a conductive pattern provided on the wiring board. One of a pair of end surfaces of the first monolithic ceramic capacitor is opposed to one of the width-direction side surfaces as a pair of side surfaces of the second monolithic ceramic capacitor with the mold resin layer interposed.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 23, 2017
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO
  • Publication number: 20170278638
    Abstract: A composite electronic component includes a capacitor device and a resistor device disposed on one another in a heightwise direction. The capacitor device includes a capacitor body, a first external electrode, and a second external electrode. The resistor device includes a base portion, a resistor body, a first upper surface conductor, a second upper surface conductor, a first lower surface conductor, a second lower surface conductor, a first end surface connection conductor, and a second end surface connection conductor. An upper surface of the base portion of the resistor device faces a lower surface of the capacitor body of the capacitor device, the first upper surface conductor and the first external electrode are electrically connected, and the second upper surface conductor and the second external electrode are electrically connected.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 28, 2017
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Shinichiro KUROIWA
  • Publication number: 20170171980
    Abstract: An electronic component containing substrate includes a substrate, a first electronic component mounted on a main surface of the substrate, and an embedment layer provided on the main surface of the substrate and embedding the first electronic component. The first electronic component is a multilayer ceramic capacitor including a ceramic multilayer body including a layered portion and a first side portion and a second side portion between which the layered portion lies and having two end surfaces opposed to each other and side surfaces connecting the two end surfaces to each other. The first side portion is located between the layered portion and the main surface of the substrate in a direction of thickness which is a direction perpendicular to the main surface of the substrate. The embedment layer is smaller in elastic modulus than the substrate.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Masaru TAKAHASHI, Choichiro FUJII, Hirobumi ADACHI
  • Patent number: 9666374
    Abstract: A capacitor component includes an element assembly, a first external electrode, and a second external electrode. The element assembly includes first and second internal electrode layers, a first connecting conductive layer extending along a fifth outer surface of the element assembly and connected to each of the first internal electrode layers, a first covering insulating layer covering the first connecting conductive layer, a second connecting conductive layer extending along a sixth outer surface of the element assembly and connected to each of the second internal electrode layers, and a second covering insulating layer covering the second connecting conductive layer. Only a portion of the first internal electrode layers are extended to the third outer surface and connected to the first external electrode, and only a portion of the internal electrode layers are extended to the fourth outer surface and connected to the second external electrode.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 30, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kazuo Hattori
  • Patent number: 9653214
    Abstract: In a laminated capacitor, a distance between an inner internal electrode at a first principal surface side, from a pair of internal electrodes that sandwich an effective dielectric layer located closest to a second principal surface side in a first sub-electrostatic capacitance portion, and a second principal surface is smaller than or equal to a distance between an internal electrode located closest to the second principal surface side in a main electrostatic capacitance portion and the inner internal electrode.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 16, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Hirobumi Adachi
  • Patent number: 9633791
    Abstract: A monolithic capacitor includes a multilayer body including a plurality of stacked dielectric layers, first and second capacitor electrodes inside the multilayer body, and outer electrodes on at least one surface of the multilayer body. The first and second capacitor electrodes are arranged perpendicularly or substantially perpendicularly to first and second surfaces of the multilayer body. The first capacitor electrode includes a capacitor portion opposed to the second capacitor electrode with the dielectric layer interposed therebetween, a lead portion connected to one outer electrode, and an intermediate portion not opposed to the second outer electrode. The second capacitor electrode includes a capacitor portion opposed to the first capacitor electrode with the dielectric layer interposed therebetween, and a lead portion connected to the other outer electrode.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 25, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Patent number: 9633786
    Abstract: A multilayer capacitor includes a multilayer body including a dielectric layer, first through third inner electrodes, and first and second capacitor sections, and first through third outer electrodes on surfaces of the multilayer body. The first capacitor section is electrically connected between the first and second outer electrodes. The second capacitor section is electrically connected between the second and third outer electrodes. The first, second, and third inner electrodes are connected to the first, second, and third outer electrodes, respectively. The first and third inner electrodes oppose each other with the dielectric layer therebetween, thus defining the first capacitor section. The second and third inner electrodes oppose each other with the dielectric layer therebetween, thus defining the second capacitor section.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 25, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazuo Hattori
  • Patent number: 9620288
    Abstract: A chip-component structure includes an interposer and a multilayer capacitor mounted thereon. The interposer includes a substrate, a component connecting electrode, an external connection electrode, and a side electrode. The component connecting electrode and the external connection electrode are electrically connected by the side electrode. The component connecting electrode is joined to an external electrode of the multilayer capacitor. The substrate includes a communication hole that communicates between opposite spaces opening in both principal surfaces of the substrate.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 11, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Publication number: 20170064834
    Abstract: A collective substrate for resistor devices includes a base, a first conductive pattern in a to-be-product region and a to-be-cut-away region of the base, and a resistive element in the to-be-product region of the base. The to-be-cut-away region includes a first region adjacent to the to-be-product region in a first direction, and a second region adjacent to the to-be-product region in a second direction. The first conductive pattern includes a first terminal portion connected to the resistive element and disposed in the to-be-product region, a first electrode portion disposed in the first region and larger in area than the first terminal portion, and a first interconnect portion extended from the first terminal portion toward the second region to be connected to the first electrode portion.
    Type: Application
    Filed: August 18, 2016
    Publication date: March 2, 2017
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Shinichiro KUROIWA
  • Patent number: 9558890
    Abstract: An electronic component includes a laminated capacitor and a substrate-type terminal on which the laminated capacitor is mounted, with an viscoelastic resin located in a space between the laminated capacitor and the substrate-type terminal. The substrate-type terminal includes a substrate body, component connecting electrodes to mount the laminated capacitor are located on a component mounting surface of the substrate body, and external connecting electrodes to be connected to a circuit board are located on a substrate mounting surface of the substrate body.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 31, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Patent number: 9560764
    Abstract: A chip-component structure includes an interposer on which a multilayer capacitor is mounted. The interposer includes component connecting electrodes, external connection electrodes, side electrodes, and in-hole electrodes. The component connecting electrodes and the external connection electrodes are electrically connected by the side electrodes and the in-hole electrodes. Outer electrodes of the capacitor are joined to the component connecting electrodes.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Patent number: 9552923
    Abstract: A multilayer ceramic capacitor includes flat inner electrodes that are laminated on each other. An interposer includes a substrate that is larger than the multilayer ceramic capacitor. A first mounting electrode to mount the multilayer ceramic capacitor is located on a first principal surface of the substrate, and a first external connection electrode for connection to an external circuit board is located on a second principal surface. A recess is located in a side surface of the interposer. A connecting conductor is located in the wall surface of the recess. The connecting conductor is located at a position spaced apart by a predetermined distance from the side surface of the interposer.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 24, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto