Patents by Inventor Kazuo Kobayashi

Kazuo Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090076224
    Abstract: The present invention provides a novel fluorine-containing rubber composite material having both of excellent fuel impermeability and excellent cold resistance, a fuel impermeable sealing material comprising the composite material and a process for preparing the composite material. The fluorine-containing rubber composite material comprises crosslinked particles of fluorine-containing silicone rubber dispersed in a fluorine-containing rubber. It is preferable that the fluorine-containing rubber comprises a vinylidene fluoride/tetrafluoroethylene/perfluoro vinyl ether copolymer, and the composite material has cold resistance of not more than ?35° C. and fuel permeability of not more than 500 g·mm/m2·day. The fuel impermeable sealing material comprises the composite material. The process for preparing the composite material comprises a step for co-coagulation of a fluorine-containing rubber emulsion and an emulsion of crosslinked fluorine-containing silicone rubber.
    Type: Application
    Filed: March 14, 2007
    Publication date: March 19, 2009
    Applicants: DAIKIN INDUSTRIES, LTD., DOW CORNING CORPORATION
    Inventors: Mitsuru Kishine, Hirofumi Nishibayashi, Toshiki Ichisaka, Kazuo Kobayashi, Ryuji Tachibana, Tadashi Okawa, Katsumi Kihara
  • Publication number: 20090065922
    Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11?). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
    Type: Application
    Filed: September 23, 2008
    Publication date: March 12, 2009
    Inventors: Moriyoshi NAKASHIMA, Kazuo Kobayashi, Natsuo Ajika
  • Publication number: 20090068702
    Abstract: The present invention relates to a means for generating a mucin-type glycopeptide or glycoprotein on a large scale in yeast. Specifically, the invention relates to a method which comprises introducing into a yeast at least one selected from the group consisting of a gene encoding UDP-GalNAc synthetase, a gene encoding UDP-GalNAc transporter, and a gene encoding polypeptide:O-GalNAc transferase, and, if desired, a gene encoding a mucin-type glycopeptide; and producing a mucin-type glycoprotein having O-GalNAc by use of the yeast.
    Type: Application
    Filed: February 26, 2007
    Publication date: March 12, 2009
    Inventors: Yasunori CHIBA, Kou Amano, Yoshifumi Jigami, Kazuo Kobayashi
  • Patent number: 7502013
    Abstract: A pointing device including a base section, an operating section shiftably supported on the base section, a magnet carried on one of the base section and the operating section, and a magneto-electro transducer carried on the other of the base section and the operating section at a location close to the magnet. The operating section includes a first part securely holding one of the magnet and the magneto-electro transducer and supported on the base section shiftably in a desired horizontal direction relative to the base section, and a second part connected to the first part and elastically biasing the first part toward a home position in a horizontal shifting range during a period when the first part is horizontally shifted along the base section.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 10, 2009
    Assignee: Fujitsu Component Limited
    Inventors: Takeshi Nishino, Shuji Nakamura, Koichi Kiryu, Kazuo Kobayashi
  • Patent number: 7502014
    Abstract: A pointing device including a base section, an operating section shiftably supported on the base section, a magnet carried on one of the base section and the operating section, and a magneto-electro transducer carried on the other of the base section and the operating section at a location close to the magnet. The operating section includes a first part securely holding one of the magnet and the magneto-electro transducer and supported on the base section shiftably in a desired horizontal direction relative to the base section, and a second part connected to the first part and elastically biasing the first part toward a home position in a horizontal shifting range during a period when the first part is horizontally shifted along the base section.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: March 10, 2009
    Assignee: Fujitsu Component Limited
    Inventors: Takeshi Nishino, Shuji Nakamura, Koichi Kiryu, Kazuo Kobayashi
  • Publication number: 20090038152
    Abstract: A method for producing an ink-jet head includes forming a buffer layer on an upper surface of a vibration plate, and forming a piezoelectric precursor layer on an entire upper surface of a surface layer, the piezoelectric precursor layer being converted into a piezoelectric sheet. The buffer layer is formed of a material with which mutual diffusion between the piezoelectric precursor layer and the buffer layer is hardly caused as compared with mutual diffusion between the piezoelectric precursor layer and the vibration plate with which no buffer layer is provided. A stack, in which the buffer layer and the piezoelectric precursor layer are formed, is heated at a predetermined temperature, and the piezoelectric precursor layer is calcinated to form the piezoelectric sheet. It is possible to suppress the deterioration of the performance of the piezoelectric member.
    Type: Application
    Filed: September 25, 2008
    Publication date: February 12, 2009
    Applicant: Brother Kogyo Kabushiki Kaisha
    Inventors: Hiroaki Wakayama, Kazuo Kobayashi
  • Patent number: 7489296
    Abstract: A pointing device including a base section, an operating section shiftably supported on the base section, a magnet carried on one of the base section and the operating section, and a magneto-electro transducer carried on the other of the base section and the operating section at a location close to the magnet. The operating section includes a first part securely holding one of the magnet and the magneto-electro transducer and supported on the base section shiftably in a desired horizontal direction relative to the base section, and a second part connected to the first part and elastically biasing the first part toward a home position in a horizontal shifting range during a period when the first part is horizontally shifted along the base section.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: February 10, 2009
    Assignee: Fujitsu Component Limited
    Inventors: Takeshi Nishino, Shuji Nakamura, Koichi Kiryu, Kazuo Kobayashi
  • Patent number: 7479729
    Abstract: A piezoelectric actuator 3 includes a metallic vibration plate 30, an insulating layer 31, a plurality of individual electrodes 32, a piezoelectric layer 33 and a common electrode 34. The insulating layer 31 is formed on the top surface of the vibration plate 30. The individual electrodes 32 are formed on the top surface of the insulating layer 31. The piezoelectric layer 33 is formed on the top surfaces of the individual electrodes 32. The common electrode 34 is formed on the top surface of the piezoelectric layer 33 over the individual electrodes 32. A plurality of terminals 36 and a plurality of wirings 35 are formed on the top surface of the insulating layer 31. Each of the terminals 36 is associated with one of the individual electrodes 32. Each of the wirings 35 connects one of the individual electrodes 32 and the associated terminal 36.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: January 20, 2009
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Hiroto Sugahara, Kazuo Kobayashi
  • Patent number: 7470474
    Abstract: A magnetic recording medium which is provided on a nonmagnetic substrate 1 with at least an orientation-controlling layer 3 for controlling the orientation of a layer formed directly thereon, a perpendicularly magnetic layer 4 having an easily magnetizing axis oriented mainly perpendicularly relative to the nonmagnetic substrate 1, and a protective layer 5 and characterized in that the perpendicularly magnetic layer 4 includes two or more magnetic layers, that at least one of the magnetic layers is a layer 4a having Co as a main component and containing Pt as well and containing an oxide and that at least another of the magnetic layers is a layer 4b having Co as a main component and containing Cr as well and containing no oxide.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: December 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Sakawaki, Kenji Shimizu, Kazuo Kobayashi, Hiroshi Sakai, Soichi Oikawa, Takeshi Iwasaki, Tomoyuki Maeda, Futoshi Nakamura
  • Patent number: 7466526
    Abstract: A ferromagnetic tunnel junction is disclosed. The ferromagnetic tunnel junction includes a pinned magnetic layer, a tunnel insulating film formed on the pinned magnetic layer, and a free magnetic multilayer body formed on the tunnel insulating film. The free magnetic multilayer body includes a first free magnetic layer, a diffusion barrier layer, and a second free magnetic layer stacked in this order on the tunnel insulating film. The first free magnetic layer and the second free magnetic layer are ferromagnetically coupled with each other. The diffusion barrier layer inhibits the additive element contained in the first free magnetic layer from diffusing into the second free magnetic layer.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: December 16, 2008
    Assignee: Fujitsu Limited
    Inventors: Masashige Sato, Shinjiro Umehara, Hiroshi Ashida, Kazuo Kobayashi
  • Publication number: 20080300365
    Abstract: The present invention relates to a fluorine-containing resin composition for molding comprising a fluorine-containing resin (A) and a hydrofluoric acid scavenger (B), in which the hydrofluoric acid scavenger (B) is organopolysiloxane. According to the present invention, a fluorine-containing resin composition which can reduce an amount of hydrofluoric acid released from a fluorine-containing resin and inhibits corrosiveness can be provided.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 4, 2008
    Applicants: DAIKIN INDUSTRIES, LTD., DAIKIN AMERICA, INC., DOW CORNING TORAY CO., LTD., DOW CORNING CORPORATION
    Inventors: Katsuhide Ohtani, Tsuyoshi Ono, Haruhisa Masuda, Ron Klein, Masakazu Irie, Kazuo Kobayashi, Igor Chorvath, Tatyana Collins, Lauren Tonge
  • Publication number: 20080265433
    Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 30, 2008
    Inventors: Moriyoshi NAKASHIMA, Kazuo Kobayashi, Natsuo Ajika
  • Patent number: 7438776
    Abstract: A method and an apparatus for adhering a tape (3) on a wafer (20) are disclosed. The wafer is supported on a table (31), and the tape is supplied, between a tape adhering surface (20?) and a tape adhering unit (46), from a tape supply unit (42). The table is moved toward the tape adhering unit, whereby the tape adhering surface of the wafer on the table is pressed against the tape adhering unit through the tape with a force (F). Further, the tape adhering unit is moved from one end (28) to the other end (29) of the wafer in parallel to the tape adhering surface. The pressure (P) under which the tape adhering surface is in contact with the tape adhering unit through the tape is kept substantially uniform while the tape adhering unit moves from one end to the other end of the wafer. As a result, the pressure on the wafer is accurately equalized in spite of the movement of the tape adhering unit.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: October 21, 2008
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Kazuo Kobayashi, Minoru Ametani
  • Patent number: 7420206
    Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 2, 2008
    Assignee: Genusion Inc.
    Inventors: Moriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
  • Patent number: 7399803
    Abstract: A composite cured silicone powder comprising: cured silicone powder (A) that has an average particle size of 0.1 to 500 micrometers; an inorganic fine powder (B) coated on the surface of said cured silicone powder (A); and a surface-active agent (C) coated on the surface of said inorganic fine powder (B); a method for producing the composite cured silicone powder which comprises the step of mixing the following components under conditions of mechanical shearing: (A) a cured silicone powder that has an average particle size of 0.1 to 500 micrometers, (B) an inorganic fine powder, and (C) a surface-active agent.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: July 15, 2008
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Yoshitsugu Morita, Kazuo Kobayashi
  • Patent number: 7382643
    Abstract: The magnetoresistive effect element comprises a pinned magnetic layer 16 having a multilayered synthetic antiferromagnet (SAF) structure, a nonmagnetic spacer layer 18 formed on the pinned magnetic layer 16, a free magnetic layer 20 formed on the nonmagnetic spacer layer 18 and formed of a single ferromagnetic layer, a nonmagnetic spacer layer 22 formed on the free magnetic layer 20, and a pinned magnetic layer 24 of a multilayered SAF structure formed on the nonmagnetic spacer layer 22, wherein a magnetization direction of the ferromagnetic layer 16c of the pinned magnetic layer 16, which is nearest the free magnetic layer 20, and a magnetization direction of the ferromagnetic layer 24a of the pinned magnetic layer 24, which is nearest the free magnetic layer 20, are opposite to each other.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: June 3, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Ashida, Masashige Sato, Shinjiro Umehara, Kazuo Kobayashi
  • Publication number: 20080121878
    Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
    Type: Application
    Filed: July 12, 2006
    Publication date: May 29, 2008
    Inventors: Moriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
  • Publication number: 20080078217
    Abstract: A lock unit used for an electronic apparatus that includes a foldable and unfoldable housing that has a first surface that is foldable, and a second surface orthogonal to the first surface includes a lock member that locks the housing in a folded state, an operation member that moves the lock member and releases a lock of the housing by the lock member, and a transmission mechanism that transmits a driving force applied to the operation member to the lock member by changing an operating direction of the operation member to another direction, and moves the lock member in the other direction, wherein the operation member is provided on the second surface, and an operating direction of the operation member is a first direction perpendicular to the second surface, the lock member projecting in a second direction orthogonal to the first surface, and a moving direction of the lock member being a third direction orthogonal to the first and second directions.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Minoru Kumagai, Ikki Tatsukami, Kazuo Kobayashi, Wataru Tanaka, Kaigo Tanaka
  • Publication number: 20080079921
    Abstract: An illumination apparatus and an exposure apparatus that achieves higher quality exposure to light and higher operating speed even where the ratio Hx/Hy between the transverse dimension Hx and the longitudinal dimension Hy of the plane of optical modulation of a two-dimensional optical space modulator is 1.5 or above, for instance, are to be provided. The focal distance fx in an x-direction and the focal distance fy in a y-direction of a second optical system that guides light emitted from an integrator to a two-dimensional optical space modulator are made different, in a ratio of fx/fy=1.6, for instance. In this way, the number of rod lenses in the integrator can be made equal between transverse and longitudinal directions and the value of Hx/Hy can be made 2.5 by bringing the aspect ratio dx:dy of rod lenses to 1.6:1, close to 1.
    Type: Application
    Filed: August 16, 2007
    Publication date: April 3, 2008
    Applicant: Hitachi Via Mechanics, ltd.
    Inventors: Yoshitada Oshida, Kazuo Kobayashi
  • Patent number: 7350350
    Abstract: In an exhaust gas purifying apparatus for a diesel engine having a diesel particulate filter (DPF) provided in an exhaust pipe, a temperature of the DPF is indirectly detected (presumed) to prevent an over-heat of the DPF during a re-generation operation thereof. For that purpose, the DPF is hypothetically divided into multiple cells, the temperature at the respective cells is presumed based on a heat budget of the cell, and the maximum temperature among those multiple presumed temperatures is controlled to be lower than a predetermined value.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 1, 2008
    Assignee: Denso Corporation
    Inventors: Shinichiro Okugawa, Kazuo Kobayashi