Abstract: An object of the present invention is to provide compounds having potent antitumor activity.

Abstract: An object of the present invention is to provide compounds which have antitumor activity and do not change cytomorphosis.

Abstract: An object of the present invention is to provide compounds which have antitumor activity and do not change cytomorphosis. Disclosed are compounds represented by formula (I) and a pharmaceutically acceptable salts and solvates thereof and pharmaceutical compositions comprising said compounds: wherein X and Z each independently represent CH or N; R1 to R3 represent H, substituted alkoxy, unsubstituted alkoxy or the like; R4 represents H; R5 to R8 represent H, halogen, alkyl, alkoxy, alkylthio, nitro, or amino, provided that R5 to R8 do not simultaneously represent H; R9 and R10 represent H, alkyl, or alkylcarbonyl; and R11 represents alkyl, alkenyl, alkynyl, or aralkyl.

Abstract: A first demultiplexer (11) and a second demultiplexer (12) receive and demultiplex STM-64 data to generate parallel data. A FEC frame generating encoder (13) carries out error correction encoding operation in a column direction of the parallel data that constitutes a matrix, adds a resulting error correcting code to the parallel data, carries out error correction encoding operation in a row direction of the parallel data, and further adds a resulting error-correcting code to the parallel data. A first multiplexer (14) and a second multiplexer (15) multiplex the error-correction-encoded parallel data, and output the data as a FEC frame.

Abstract: An optical receiver includes a soft-decision deciding means (7) for deciding an electric received signal according to a plurality of decision levels so as to output a multivalued decision signal, a demultiplexing means (5) for serial-to-parallel converting the multivalued decision signal so as to output a multivalued parallel signal, a soft-decision error correction decoding means (8) for making an error correction to the multivalued parallel signal based on reliability information so as to output an error-corrected parallel received signal and decision results indicating the decision of the electric received signal according to the plurality of decision levels, a probability density distribution estimation means (9) for estimating probability density distributions based on distributions of the decision results indicating the decision of the electric received signal according to the plurality of decision levels, and a decision level control means (10) for controlling the plurality of decision levels in the so

Abstract: An optical-electrical (OE) conversion unit (11) converts optical signals received through an optical transmission line into first electrical signals and second electrical signals. A multilevel identification unit (12) identifies the first electrical signals based on a plurality of identification levels, and produces multinary identification signals. A serial-parallel conversion circuit (13) converts the multinary identification signals into multinary parallel signals. An optical reception quality circuit (14) produces reliability information that indicates quality of optical signals from the second electrical signals. An error-correction decoding circuit (15) corrects errors based on the multinary parallel signals and the reliability information, and outputs error-corrected parallel signals.

Abstract: A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.

Abstract: An object of the present invention is to provide compounds having potent antitumor activity.

Abstract: An optical transceiver 1 comprises first and second pseudo-random pattern generators 23 and 28 for generating a pseudo-random pattern signal, which are placed in a transmitting side path 6 and in a receiving side path 11 of the optical transceiver 1, respectively; first and second pseudo-random pattern detectors 21 and 26 for evaluating an inputted pseudo-random pattern signal, which are placed in the transmitting side path 6 and in the receiving side path 11 of the optical transceiver 1, respectively; a first loopback path 31 that loops back from a multiplexing circuit 3 to a demultiplexing circuit 8; and a second loopback path 32 that loops back from a light-electricity converter 7 to an electricity-light converter 4.

Abstract: In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is rechanged to an original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct an error of information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct a residual error of information, and the order is rechanged to an original order by a second interleaving circuit 37.

Abstract: An FEC multiplexing circuit (2) has a configuration in which a first memory circuit (15) is arranged on the input stage of a first RS encoding circuit (16), a second memory circuit (17) is arranged on the input stage of a second RS encoding circuit (18), error correction encoding is performed by a combination of different data having two directions, and thereafter, error correction codes are multiplexed to generate an FEC frame. On the other hand, an FEC demultiplexing circuit (6) has a configuration in which a third memory circuit (42) is arranged on the output stage of a first RS decoding circuit (41), a fourth memory circuit (44) is arranged on the output stage of a second RS decoding circuit (43), error correction is performed by a combination of different data having two directions, and, thereafter, parallel data read from the fourth memory circuit (44) are multiplexed to reproduce original information data.

Abstract: The data transmission and reception system comprises a data transmitter and a data receiver. The data transmitter generates and transmits a high-speed serial signal through a transmission path and the data receiver receives the serial signal. The data transmitter, when forming the frame for every tributary signal, inserts into the frame a frame bit indicating a boundary of the frame and, after having formed the frame, performs only a bit synchronization with respect to every tributary signal. On the other hand, the data receiver, for a respective tributary signal, stores a data indicated by the tributary signal and, in a timing based on a detection of the frame bit of the tributary signal and a reference frame pulse commonly issued between tributary signals, outputs the stored data to thereby perform the tributary synchronization.

Abstract: The present invention relates to a process for producing a 4-quinolone derivative, comprising allowing an o-aminoacetophenone derivative to react with a formic acid in an aprotic solvent in the presence of a suitable base, and adding a protic solvent to the reaction mixture. This is a simple process for producing 4-quinolone derivatives, applicable to large-scale commercial production.

Abstract: The present invention relates to novel quinoline derivatives and quinazoline derivatives represented by the following formula (I): ##STR1## [wherein R.sub.1 and R.sub.2 are each independently H or C.sub.1 -C.sub.4 -alkyl, or R.sub.1 and R.sub.2 together form C.sub.1 -C.sub.3 -alkylene, X is O, S or CH.sub.2, W is CH or N, and Q is a substituted aryl group or substituted heteroaryl group] and their pharmaceutically acceptable salts, having platelet-derived growth factor receptor autophosphorylation inhibitory activity, to pharmaceutical compositions containing these compounds, and to methods for the treatment of diseases associated with abnormal cell growth such as tumors.

Abstract: An air compressor includes a compressor unit, an intake regulator valve connected to the compressor unit, and intake filter connected to the intake regulator valve, an oil separator connected to the compressor unit, an oil supply line connecting the lower part of the oil separator to various points inside the compressor unit, and an oil return line connecting the oil collector unit to the passage connecting the intake filter and the intake regulator valve. The passage connecting the intake filter to the intake regulator valve has a section of reduced cross-sectional area, including an inner tube having holes to connect to a surrounding hollow region. The oil return line opens into the passage at a point higher than the level of oil in the intake regulator valve.

Abstract: An oil-cooled air compressor in which a control unit effects operation of the compressor unit in the condition that a specified period of time has elapsed since the last time the compressor unit was operated for a specified period of time or more at a temperature greater than a specified temperature, to thereby effect dewatering operation of the separator of the compressor only when necessary, resulting in the reduction of wasteful consumption of energy.

Abstract: This invention provides a package-type oil-cooled air compressor in which the housing is divided into two chambers, in one of which, a first chamber, are located the compressor unit, motor used to drive the compressor unit, air intake filter and intake regulator valve connected to the compressor unit, and in the other of which, a second chamber, are located the oil cooler and sirocco fan. An air duct connects the two chambers. Air outlets are formed in each of the chambers and an air inlet is formed in the second chamber. Air is introduced through the rotation of the sirocco fan into the second chamber via the air inlet. A portion of this air is directed into the first chamber via the air duct where a part is used to supply the compressor unit and the remainder flows over the components located in the first chamber to cool them and leaves via the outlet formed in the first chamber.

Abstract: A frame alignment circuit including at least a first series-to-parallel data converter having a shift register for accumulating series data, a latch circuit for converting the accumulated data into parallel data and a variable counter for dividing a clock signal into a divided clock signal. The frame alignment circuit further includes a pattern detector which detects a frame alignment pattern of the parallel data, a determining circuit which determines a deviation of alignment based on a reference frame alignment signal and the detected frame alignment pattern and a shift controlling circuit for controlling at least a dividing ratio of the variable counter based on a deviation of alignment signal output by the frame alignment circuit.

Abstract: A first frame counter generates a position signal for an input subframe address which is synchronized with an input clock signal based on an input frame phase signal. The first frame counter also generates a write address enabling signal. A subframe type detector generates a write/read control signal based on an input frame signal. Depending upon the position signal for the input subframe address, the write address enabling signal and the write/read control signal, a first subframe phase synchronization device and a second to nth subframe phase synchronization device control a buffer corresponding to 1/m of a frame data amount by a write address, where m (n>=m) is a multiplexing number. The first subframe phase synchronization device and the second to mth subframe phase synchronization device writes data corresponding to a first to mth input subframe signal based on the input frame signal into a buffer respectively. An input relative phase is synchronized with a standard relative phase.

Abstract: A frame alignment circuit comprises a first series-to-parallel data converting means comprising a first shift register for accumulating a series data, a first latch circuit for converting the series data into a first parallel data and a first counter for dividing a clock signal into a divided clock signal; a second series-to-parallel data converting means comprising a second shift register for accumulating the first parallel data outputted from the first series-to-parallel data converting means, a second latch circuit for latching the first parallel data and outputting the first parallel data which is converted into a second parallel data and a second counter for further dividing the divided clock signal of the first counter; a frame alignment determining means for detecting a deviation of alignment based on a frame alignment pattern; and a shift controlling means for controlling at least a divided ratio of the second counter based on the deviation of alignment outputted by the frame alignment determining mea